* Handle the three other timer interrupts for now, from the AR724x
  later.  If the interrupts are ACKed even if they're not masked, we get
  the interrupts again later.  Grr.

* The AR724x and later chips want the interrupt bits cleared by writing the
  relevant bit to it, NOT by writing all but the current interrupt to it.

Tested:

* AR9344, DB120 reference board

TODO:

* Test ar724x and later chips to ensure no regressions have occured.
The AR71xx has APB interrupts in the MISC registers from 0-7, later
chips have more.

So for now, let's allow more.  We should teach the apb code to just
reject interrupts that lie outside what the chip can do at runtime.