less transmission per sec, added needed sigals to sensitivity list (combinatorial structure)
removed old idea
data updated sequentially - very well seen on LED's with small baud
uart rewrite, better results. Problem with edge synch - consider having prescaler in reset all time except transmission
added reciever module
Project now integrates both Tx and Rx (switch between them with a switch) - works well even up to 70 Mbps (usart)
code generation and check
use of 3 PLL's
data sending via switches or generator (decision based on SW14)
added receiver module (shows transmission errors)
error checking
usart added range
new PLL values
3 PLL's
added LVDS, to test
vivado problems with syntesis... (failed to route)