southbridge/hudson: Use MMIO instead of PIO to access PM space

The MMIO region is set up by AGESA very early on, so we can use it to
access the PM register space in ramstage. 16-bit accessors are also
provided to simplify some setup tasks. 16-bit accesses are not
possible via PIO.
The pm2_iowrite/read accessors are removed, as they are not used.

Change-Id: Ie7967b5086eb004525c39721338c6495aedc8165
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5503
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
cpu/amd/agesa/family15tn: Add initial support for SMM mode

This is the minimal setup needed to be able to execute SMI handlers.
Only support for ASEG handlers is added, which should be sufficient
for Trinity (up to 4 cores).

There are a few hacks which need to be introduced in generic code in
order to make this work properly, but these hacks are self-contained.
They are a not a result of any special needs of this CPU, but rather
from a poorly designed infrastructure. Comments are added to explain
how such code could be refactored in the future.

Change-Id: Iefd4ae17cf0206cae8848cadba3a12cbe3b2f8b6
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
cpu/amd/agesa/family15tn: Add udelay implementation for SMM

This is a small implementation which uses only MSRs and rdtsc, without
relying on northbridge or other system hardware. It's SMM safe in that
it only reads registers, and doesn't modify the state of the hardware.

Change-Id: Ifa02ca73455b382f830c9b30b80b4f1bb18706b4
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
southbridge/amd/agesa/hudson: Add initial support for SMM

This sets up the infrastructure to handle SMIs generated by the Hudson
southbridge. An API for interfacing to mainboard handlers is not
defined at this point. A few functions are defined to allow mainboard
code to enable SMIs from GEVENT pins. These are the only functions which
I expect to be needed anytime in the foreseeable future.

SMIs are always acknowledged and cleared, as not clearing an SMI will
cause us to re-enter the SMI, effectively bricking the machine if a
southbridge-generated SMI without a handler occurs.

Change-Id: Ibceb21ac5423eb134d3eb7d24800280b183f7619
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
southbridge/hudson: Pass GEVENT SMIs to mainboard_smi_gpi()

Change-Id: Ifc368974a7a0dc0756431654fb89668e3846801a
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
southbridge/hudson: Add support for ACPI enable/disable via SMI

This enables the ACPI SMI command port in the FADT table, and sets up
the hardware accordingly. If we have SMI enabled, then we don't set
the SCI_EN bit at boot, causing the OS to send the ACPI_ENABLE
command, as required by the ACPI spec. This gives us a chance to hook
into the mainboard_smi_apmc() handler.

Change-Id: Ib4c63d55b3132578dcae48bfe2092d4ea35821dd
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
hp/pavilion_m6_1035dx: Add SMI handler and handle EC requests

The EC may disable some functionality, such as Caps Lock LED and
battery charging if it never receives a command to go in APM mode. If
we start it in APM mode, then immediately switch to ACPI mode, it will
not get its SCIs serviced until an ACPI OS boots. If its SCIs are not
serviced, it may assume the OS has hung.

The way we solve this is to initalize the EC in APM mode, and only
switch it to ACPI when an ACPI-capable OS issues the ACPI_ENABLE
command. The switch has to be handled in SMM.

Although we aren't yet processing SMIs from the EC, we are reading the
status in order to satisfy the EC that the event is handled.

Change-Id: Iffaeb9a6f57841f456c4bce8337dc09b287f8758
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
[RFC] ec/compal/ene932: Update to use coreboot EC API

This is based on the EC-mainboard interaction draft specification [1]

Enjoy the clusterURL in clustercommit clustermessage.

[1] http://www.coreboot.org/ACPI/Board-EC_interaction#The_mainboard_namespace_method

Change-Id: If0b09be4f5e17cc444539a30f0186590fa0b72b5
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
hp/pavilion_m6_1035dx: Implement ACPI for wireless toggle hotkey

Change-Id: I2e9ab68263648af8c9d46999e960f0a0711b61d7
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
hp/pavilion_m6_1035dx: Implement MB.LIDS ACPI method

Change-Id: I654ca745f7404b86aa25fb2e696751d616d0ca03
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
usbdebug: Reduce bus reset delays

According to EHCI specification, host controller software stops
the USB Reset condition by writing PORT_RESET=0. Software then
poll-waits this bit until controller hardware has completed USB
Reset sequence and read returns with PORT_RESET==0.

Change-Id: I6033c4d904c2af9eb16f5f3c1eb825776648cc1d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
usbdebug: Add optional quirk for old DIY debug part

Not sure what this is about. Required for FX2.

Change-Id: I86878f8f570911ed1ed3ec844c232ac91e934072
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
vendorcode/amd/agesa/fam15tn: Clean #includes in public headers

Right now, coreboot code using AGESA headers can only build if all the
AGESA path are given to the compiler via the "-I" option. This is sub-
optimal, as it requires us to have every AGESA source directory
specified as a compiler include path. This pollutes our global include
paths.

We restrict the compiler include paths to only allow "AGESA_ROOT/" and
"AGESA_ROOT/Include". We then modify the AGESA headers to specify
non-local include files relative to "AGESA_ROOT/Include".

We use the convention that includes relative to the directory of the
header are included as "path/to/header.h", while includes relative to
AGESA_ROOT are included as <path/to/header.h>.

This change allows building coreboot code based on AGESA with the
limited subset of include paths, but does not allow AGESA itself to
build with this restricted subset.

Change-Id: I31102273c8caa8d6b1d80774bfd35711825bec03
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
NOTFORMERGE: Add SCI map

Change-Id: Ifa50bf000cfc8e77a6a4d84752f89838f165f7a0
NOTFORMERGE: Add tons of ACPI debug info

Change-Id: I2475ba04a5258f9d8af9b987a461ec2d5ab60135
NEVERMERGE: Don't shithack _L13

Change-Id: I6538fa821a7a15a3bdbdaf9d3d0f0867585c518c
NEVERMERGE: Temporarily disable USB ctrl

Change-Id: Ie15fc912ed74b2a49ec005cc8145e88cc0e628a3
NEVERMERGE: Add SMI debugger

Change-Id: I7aff8a976d95c32b24a91940faefe4fd18a713ce
console: Drop driver list in ramstage

This framework was only available in ramstage. So we had to define
console output functions separately for bootblock, romstage and SMM.
Follow-up patches will re-enable all the consoles removed here,
in a more flexible fashion, and with less lines-of-code and copy-paste.

Also the driver list is not in a well-defined order and some of the
loops could exit without visiting all drivers.

NOTE: This build has no console in ramstage.

Change-Id: Iaddc495aaca37e2a6c2c3f802a0dba27bf227a3e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
console: Use romstage code for ramstage and SMM

Console is arch-agnostic and there is no need for separate
implementations for romstage and ramstage.

For SMM there is console only if DEBUG_SMI is selected.

Change-Id: I7028eeeff8bfbb9c8552972436b29a7508834d87
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>