Start of SAMA5D3 XPlained demo.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2272 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
Add new port layer for Cortex-A devices without the means to mask interrupt priorities.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2273 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
SAMA5D3 Xplained demo blinky running.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2274 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
Rename ARM_CAx_No_GIC ARM_CA5_No_GIC and add FreeRTOSConfig setting to specify the number of registers in the FPU unit.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2275 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
Add 'full' demo to the SAMA5 Xplained demo - but so far without interrupt nesting tests or CLI.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2276 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
Remove Zynq demo project ready to recreate the project using the 14.2 version of Xilinx's SDK.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2277 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
Add back Zynq demo - this time using SDK V14.2.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2278 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
Re-test Zynq demo now it is using the latest tools.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2279 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
Update CyaSSL to latest version.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2280 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
SAMA5D3 demo:  Add CDC driver code and use CDC to create a simple command console.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2281 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
Carry on working on SAMA5D3 demo:
- Add full interrupt nesting tests.
- Add additional critical section/context switching tests.
- Set interrupt priorities so everything can run at once without any software watchdog errors.
- Re-enable interrupts in each IRQ handler.
- Add in run-time stats.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2282 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
Continue working on the GIC-less Cortex-A5 port for IAR:
- Add in the assert when a task attempts to exit its implementing function without deleting itself.
- Remove obsolete code from the context switch asm code (obsoleted by the fact that there is no mask register).
- Attempt to make code more generic by using definitions for additional register addresses.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2283 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
Cortex-A5 IAR port baseline prior to removing all SAMA5 specifics to make it generic.:
- Slight improvement to the save context macro.
- Remove some #warning remarks.
- Enable interrupts before calling the ISR handler rather than in the ISR handler.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2284 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
Cortex-A5 IAR port:
- Removed SAMA5 specifics from the port layer, and instead call a generic ISR callback as per Cortex-A9 ports.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2285 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
Common demo tasks:
- Add additional tests to GenQTest.c to test the updated priority inheritance mechanism.
- Slightly increase some delays in recmutex.c to prevent it reporting false errors in high load test cases.

SAMA5D3 Xplained IAR demo:
- Remove space being allocated for stacks that are not used.
- Remove explicit enabling of interrupts in ISR handers as this is now done from the central ISR callback before the individual handers are invoked.
- Reduce both the allocated heap size and the stack allocated to each task.
- Enable I cache.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2286 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
General maintenance - changing comments and correcting spellings only.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2287 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
Demo application related:
+ Update the RZ IAR project so it targets the RZ RSK rather than custom hardware.
+ Update the RZ ARM/DS-5 project so it targets the RZ RSK rather than custom hardware.
+ Updated RX64M demos to use the new iodefine.h naming.

Cortex-A9 port related:
+ Update IAR, ARM and GCC Cortex-A9 port layers to include a 'task exit error' function which is called if a task attempts to incorrectly exit its implementing function.
+ Moved the instruction which switches into system mode out of the restore context macro, as it is only needed when starting the first task.

Core kernel files related:
+ Ensure there are no references to the mutexes held count when mutexes are excluded from the build.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2288 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
Remove some irrelevant CyaSSL files.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2289 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
***IMMINENT RELEASE NOTICE***
Update version numbers ready for FreeRTOS V8.1.0 release in about 10 days.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2290 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
Minor edits prior to tagging V8.1.0.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2291 1d2547de-c912-0410-9cb9-b8ca96c0e9e2