Allow some behavioral assignments to unresolved wires.

If the l-value is an unresolved wire, then elaboration can allow
the assignment as long as it is to bits that are not otherwise
driven. Handle this in some simple cases.
Handle proceedural writes to UWIRE objects.

The elaborator allows this only if it determines that the bits
that are procedural written are not also continuously written.
Account for force l-values that are uwires.
Handle packed structs as module outputs.
Fix broken search where member names accidentally match variables.
Fixed homepage link

The link was pointing to a page that said:

This page has been moved to http://iverilog.icarus.com, you will be forwarded there automatically in 3 seconds.
Please update your links.

So now it's updated
Start a sizer backend.
Collect some actual sizer statistics.
Rearrange counters to me more realistic

Instead of counting gate types, convert to gate count estimates
and some other interesting statistics. Also handling the descent
into child scopes.
More robust case statement synthesis

Handle the cases that the case statement carries complet sub-
statements. This is just a generalization of what is already
there.
Fix for GitHub issue 11 : Syntax error on operator attributes.

Attributes are allowed to be attached to unary, binary, and ternary
operators in expressions. For now just accept and discard them.
Fix for GitHub issue 8 : Signedness of constant binary bitwise operations.

When doing constant evaluation of binary bitwise operations, the result
value must be signed if the expression type is signed.
Fix for GitHub issue 7 : Undef propagation in power operator.

The vvp_vector2_t constructor that takes a vvp_vector4_t value was
documented as creating a NaN value if the supplied vector contained
any X or Z bits, but instead used the standard Verilog 4-state to
2-state conversion semantics (X or Z translate to 0). I've added an
optional second parameter to the constructor to allow the user to
choose which semantics they want, as both are needed.
Fix for GitHub issue 9 part 1 : Efficiency of vvp_vector2_t::pow() function.

The vvp_vector2_t::pow() function is recursive, and performs a multiplication
operation on each step. The multiplication operator was expanding the result
vector to accomodate the maximum possible result value for the given operand
vectors, thus causing the execution time of the power operation to be
exponentially proportional to the exponent value. Both in this case and
in general, it is unnecessary for the multiplication result vector to be
expanded, as the compiler has already determined the required vector width
during elaboration, and sizes the operand vectors to match.
Fix for GitHub issue 9 part 2 : Efficiency of the verinum pow() function.

This changes the verinum pow() function to use the more efficient algorithm
used in the vvp runtime. It will still be slow if the left operand is unsized
and the right operand is large, as it will expand the result vector to avoid
overflow.
Handle asynchronous if-without-else synthesis.
sizer support for simple LPM MUX devices.
Sizer pay attention to ivl_synthesis_off attribute.
Detect proper support for missing else_ without latches (synthesis)
Fix for GitHub issue 12 : Ternary lval-rval width mismatch.

A simple typing error that caused the expression to be incorrectly
evaluated as a real constant.