sim_core: reworked register macros and descriptor lines

reworked register macros and instruction descriptor lines to more
 closely follow avr data sheet insruction (and avr instruction wiki)
 references. register macro usage (with few exceptions) have been worked
 throughout the core to be more uniform and consistent.  most notably d
 is used nearly uniform throught the avr instruction set references,
 prior the core intermixed the usage of the opcode registers d and r
 notation.

lpm & elpm, trace bug fixed... tracing would always show lpm Z+ regardless of
 the actual operation performed...  more importantly than that, looking
 at the instruction data sheet reference, the relevant bit is bit 1
 in the opcode...  prior op was equal to opcode & 3 similar to ld/st
 instructions...  the original lpm checked for op == 1 and the
 reworked elpm checked for op == 3.  this has been corrected for
 both opcode implimentations by setting op to opcode & 1 and just
 using op to flag for post increment.

	modified:   sim/sim_core.c