Add entry to the periph file for .tcl sources

Which vivado seems to use for its simulink IP
Change MMCM parameters for Kintex 7 compat.
Parameterise ADC16 interface for arb. num of ADCs

(Which really means it probably shouldn't be called
adc16_interface anymore...)
Added ADCs and some other pins to snap
Change sysclk to 100MHz

Input to FPGA is 200 MHz, divide by 2 in MMCM
Get platform details from yaml files

Rather than manually subclassing the Platform
class in platform.py
Make SNAP have 100MHz sysclk from 200MHz input
Don't promote ports with no connections

So an instantiation with a port that doesn't go anywhere
doesn't promote a nameless signal to a top level signal or port
Get platform from yaml, buxfix to constraint index
Add yellow block for snap ADC (with 3 chips)
Add core_info.tab for snap
Add ROACH2 adc16 test model

The main test_adc16 is now a test for SNAP