ARM: 8119/1: crypto: sha1: add ARM NEON implementation

This patch adds ARM NEON assembly implementation of SHA-1 algorithm.

tcrypt benchmark results on Cortex-A8, sha1-arm-asm vs sha1-neon-asm:

block-size      bytes/update    old-vs-new
16              16              1.04x
64              16              1.02x
64              64              1.05x
256             16              1.03x
256             64              1.04x
256             256             1.30x
1024            16              1.03x
1024            256             1.36x
1024            1024            1.52x
2048            16              1.03x
2048            256             1.39x
2048            1024            1.55x
2048            2048            1.59x
4096            16              1.03x
4096            256             1.40x
4096            1024            1.57x
4096            4096            1.62x
8192            16              1.03x
8192            256             1.40x
8192            1024            1.58x
8192            4096            1.63x
8192            8192            1.63x

Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Jussi Kivilinna <jussi.kivilinna@iki.fi>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: 8118/1: crypto: sha1/make use of common SHA-1 structures

Common SHA-1 structures are defined in <crypto/sha.h> for code sharing.

This patch changes SHA-1/ARM glue code to use these structures.

Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Jussi Kivilinna <jussi.kivilinna@iki.fi>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
msm: kgsl: Elevate the priority of the thread during adreno start

It turns out that having lots of spurious threads causes race
conditions. Who knew? Instead of spawning a new high prority
thread just bump the priority of the current thread up
while adreno_start is running.

Change-Id: Ic0dedbadf65da11c800578c8769ae844f010e925
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>

Conflicts:
	drivers/gpu/msm/adreno.c
ASoC: msm: qdsp6v2: update int to size_t

Int aren't same size as size_t in 64bit kernel. This actually cause part of
the stack to be overwritten.

Change-Id: I0ebff1fb9030fdb93a6889ee02329599ae2800fb
Signed-off-by: Fred Oh <fred@codeaurora.org>
msm: compr: Use irq{save/restore} version of spinlock

compress driver event handler uses spin_lock/unlock APIs.
It should be sufficient to use the irq{save/restore} versions.

Change-Id: I8f32c6896396a09faa1baf741bd182d8ceb4301a
Signed-off-by: Haynes Mathew George <hgeorge@codeaurora.org>
ASoC: msm: compr: Ensure drain sequence is executed

This change ensures drain sequence is executed even if
a pause/resume commands are sent from userspace while
the control thread is waiting for all buffers to be consumed
by DSP.
CRs-Fixed: 711920

Change-Id: I6ffcc072e00fa1865b0484f54fa6b070c1a73cf2
Signed-off-by: Haynes Mathew George <hgeorge@codeaurora.org>
Linux 3.10.63
cpufreq: Return directly in __cpufreq_get if policy is NULL

__cpufreq_get() checks whether policy->cur matches frequency returned
by cpufreq device driver and acts accordingly. However, policy could
be NULL if the CPU is being hotplugged. Current implementation crashes
when trying to dereference the NULL policy.

Return the frequency provided by cpufreq device driver directly if
policy is not available.

Change-Id: I1f2ba4028c259392bf730db37dbec2d8c5ae3fa4
Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
cpufreq: Protect against hotplug in cpufreq_register_driver()

cpufreq_register_driver() could race with CPU hotplug during
bootup. Since hotplug notification is not registered when
subsys_interface_register() is being executed, it's possible
cpufreq's view of online CPUs becomes stale before it registers
for hotplug notification.

Register for hotplug notification first and protect
subsys_interface_register() against hotplug using
get/put_online_cpus().

Change-Id: I26b2908f1d167c2becc4e8664c357bb7c6162406
Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
msm: perf: tracectr: Initialize cnts after hotplug

Due to the mismatch between counter values saved across CPU hotplug
by perf and tracecounter logic, incorrect values are calculated
for first entry in trace buffer.
Ignore the first entry when CPU comes out of hotplug and set previous
counter values in this scenario.

Change-Id: Ieeeaa301d713f338f11f6e84aeb984a3708e45fc
Signed-off-by: Sheetal Sahasrabudhe <sheetals@codeaurora.org>
Perf: Reset pmu after hotplug

The counter enable bits were staying in undefined state after CPU
came out of hotplug when perf was not enabled.
This was resulting into non-zero values for counters in ftrace
buffer which were not enabled by perf.
Clear the pmu when CPU comes out of hotplug and perf is not enabled.

Change-Id: I31e17565ad914650a12102a5c359b363f8f2ca2a
Signed-off-by: Sheetal Sahasrabudhe <sheetals@codeaurora.org>
msm: perf: set filter bits for cycle counter on krait

When programming the cycle counter on krait, the filter
register needs to be programmed in order to set the
usermode/kernelmode filter options.

Change-Id: Ifd5b032c9a5df4821706438d4359f84d8f614468
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>

Conflicts:
	arch/arm/mach-msm/perf_debug.c
Perf: Fix hrtimer operation across hotplug

Stop hrtimer associated with CPU clock event when
core goes down. Start the timer when core comes back up.
This is needed to ensure proper software timer operation
across hotplug.

Change-Id: I027bf2718d177fa31be2a7cfe7ef98f93cb4aeda
Signed-off-by: Sheetal Sahasrabudhe <sheetals@codeaurora.org>
Perf: add perf user-mode permissions

Allow user-mode applications to use the performance
counters for debugging and performance analysis.

Change-Id: I0caed53dafb9965b8eece92762a0b67a40ff3be5
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
Perf: Add event type check in hrtimer hotplug fix

The hrtimer hotplug fix was missing event_type check due to which
the check was passing both software clock and hardware cycles.

Change-Id: I1d16d0ccc6ce27963ace9d2f3e1e1eab8f8c7d18
Signed-off-by: Sheetal Sahasrabudhe <sheetals@codeaurora.org>
Perf: Add debugfs node to clear PMU

Create debugfs node to clear PMU and some internal variables
used by Perf code. This provides a recovery path for
PMU related unexpected error scenarios.

Change-Id: I88ae9dda0888db9316ce123f6f3a58faec4d69ee
Signed-off-by: Sheetal Sahasrabudhe <sheetals@codeaurora.org>

Conflicts:
	arch/arm/Kconfig
msm: perf: reset perf cycle counter on krait

The cycle counter was not included in the list of
counters being reset. This could result in the cc
enable bit being set randomly, leading to spurious
interrupts when the counter overflowed, even though
the cc was not being used.

Change-Id: Ic7da5e78f932a25d05ce116aeec7a0709ddbb20e
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
Perf: interrupt disable without bringing cpus up

Refactor the interrupt disabling so that interrupts
are disabled when a cpu is hotplugged out, even if
there are no perf events on that cpu, but it holds
the PMU irq. This means that when perf ends it does
not have to re-enable an offline cpu just to disable
its irq.

Change-Id: Id0e052e4386173e107abe0eb6e80cb130d92ec24
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>

Conflicts:
	arch/arm/kernel/perf_event_cpu.c
Perf: stop counters when going into hotplug

Hotplug disables the pmu irq, but if counters are
running in the window before the CPU is hotplugged off
they can overflow and generate an interrupt. Because the
interrupt is disabled, this prevents the cpu from going
down which leads to a spin loop in the cpu_down driver
which consumes 100% cpu.

Events are stopped during hotplug processing. However,
perf is hooked into the timer tick, and restarts enabled
events on every tick, even if they were stopped. Change
the event state to OFF to prevent this.

Processing for stop reads the counters, so a separate call
is no longer needed. Start processing re-enables events so
the from_idle flag is not needed during pmu_enable.

Change-Id: I27ded876315147b50d9f85c09487b107a9216641
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
msm: perf: Refine disable/enable in tracecounters

Tracecounter code was not disabling counters as early as possible
and enabling them as late as possible. Refine the logic so cycles
spent inside the handler are as lower. This results in more accurate
per-process counter values.

Change-Id: Ib8bb17b1212ddf9e3d1c33a00ae486d885a36e45
Signed-off-by: Sheetal Sahasrabudhe <sheetals@codeaurora.org>

Conflicts:
	arch/arm/mach-msm/perf_debug.c