Verilog/system verilog

SystemVerilog is an extension to normal Verilog that is used mainly for system level verification.
This PR adds support for this language in the available Verilog parser.
At the moment the following is supported:

* Packages
* Programs
* Classes
* Interfaces (including modport)
* Assertions and properties
* Covergroups
* Typedefs

Various new variable types have been added, although still as part of the already available "register" and "net" kinds. It is possible that this will be modified in the future and that each variable will have its own kind.

Various simple test cases have been added, grouped by each new added functionality. It is my intention to expand these test cases whenever an issue is found/reported, which I expect to happen soon after this PR is merged.

I will keep the PR open until the weekend to allow everyone to review the changes and suggest improvements.