Extended the iris core

- Instructions are now 24 bits long
- Added two 16 bit address registers (a0 and a1)
Extensive modifications to iris core

- 16-bit registers
- 256 registers
- Instructions are 32-bits in length
- 64 8-bit implied registers (used to work around missing encoding space)
- Eliminating most macros for extracting fields
- Reworking jump instructions (not done)
- Fox ONLY...Final Destination
Simplified the encoding process further

First byte now only contains 3 bit group and 5 bit op fields. I do not
decompose them any further. I also updated all of the comments and enums in
iris.h to reflect the new encoding work.

Encode.c now only contains basic functions which we build off of to do other
things.
Fixed issues in sim.c

Code will still not compile at this point
Added a travis builder for iris
Fixed an incorrect name in encode.c
Updated readme
Renamed README to README.md
Updated readme.md
Brought more code up and running
Updated compare decoding
Added a top level makefile
travis.yml now calls top level make
Removed platform info from Makefile
Added o.phoenix to phoenix's .gitignore
Added more jump ops and fixed bugs

Added the ability to do jump.if0 and jump.if1 as we make things more flexible
that way. Added new modes to mnemonic.c and fixed sprintf bugs in unparse.c.
The bit field (: 16) in the core structure has been removed as it is redundant
in this case.
Reimplemented jump
Updated move operations
Finished implementing the rest of the misc ops
Finished extending the core of iris