Fixed some whitespace inconsistencies.
Some renaming and moving around.
Now produce an active command.
Changed to only use two clock managers.

Also produce 90 and 270 degree phase clocks for 133MHz.
Added in 90 and 270 degree clock to Ddr controller.
Added in write burst.
Added in read burst.
Added in a read state for the system.
Re-ordered the module declaration.
Made the write logic not be triggered on the positive and negative edges of the clock.
Made the dqs not require the posedge and negedge of the clock.
Further simplified the word selection for write.
Made the read not use both edges of the clock.
Removed to 25MHz clock from the DDR controller to avoid issues.
Removed the gated clock for the writing.
Removed the gated clock on dqs.
Seems to flash data read from the RAM.
Debounced the reset signal to avoid issues.
Uncommented the DDR constraints.

Also added extra specifications for the output clock.