zynq: ddrc: Setup half of memory only for ECC case

This patch is around for a while but it was lost
in past and Mike has pointed to it again.

Here is description from Mike which handle non ECC case:
While bringing up a board that uses only a single memory chip, and
hence only 16-bit DDR width, the memory size was somehow cut in half.
The cause turned out to be a line in ddrc.c that just divides the memory
size by two for no apparent reason when the bus width is 16.

The memory size is simply obtained from a constant in the configuration
header, so do not modify it. Tested this on my board and now the memory
size is correct.

Reported-by: Cayer Yves <ycayer@ciena.com>
Reported-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>