clk: rockchip: fix parent for spdif_8ch_frac on rk3288

The parent should be spdif_8ch_pre not spdif_8ch_src, which doesn't
exist and looks to be a typo.  The TRM also confirms this.

Signed-off-by: Sonny Rao <sonnyrao@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
clk: rockchip: Add CLK_SET_RATE_PARENT to aclk_cpu_pre

We'd like to be able to call clk_set_rate() on aclk_cpu (a gate) at
bootup.  In order for this to have any effect we need its parent
(aclk_cpu_pre) to percolate the rate change to _its_ parent
(aclk_cpu_src).  Add CLK_SET_RATE_PARENT to make this happen.

Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
clk: rockchip: add 400MHz and 500MHz for rk3288 clock rate

This patch add 400MHz and 500MHz to clock rate table for rk3288.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
clk: rockchip: rk3288: removing the CLK_SET_RATE_PARENT from i2s_clkout

Removing the CLK_SET_RATE_PARENT from i2s_clkout, to limit i2s0_clkout
to select between its two parent without being able influence the core
i2s clock.

Tested on rk3288 board, suggested by Heiko.

Signed-off-by: Jianqun <jay.xu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
clk: rockchip: add npll to source of sclk_gpu

The possible sources for the rk3288-gpu-clock also include the npll,
making it the same list of sources as for uart0.

This patch make a common source for uart0 pll src and sclk_gpu,
so that gpu can get its clock from npll.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
clk: sunxi: make factors clock mux mask configurable

Some of the factors-style clocks on the A80 have different widths
for the mux values in the registers.

Add a .muxmask field to clk_factors_config to make it configurable.
Passing a bitmask instead of a width parameter will allow reuse
in case we support table-based muxes in the future.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
clk: sunxi: Add support for A80 basic bus clocks

The A80 SoC has 12 PLL clocks, 3 AHB clocks, 2 APB clocks, and a
new "GT" bus, which I assume is some kind of data bus connecting
the processor cores, memory and various busses. Also there is a
bus clock for a ARM CCI400 module.

As far as I can tell, the GT bus and CCI400 bus clock must be
protected.

This patch adds driver support for peripheral related PLLs and
bus clocks on the A80. The GT and CCI400 clocks are added as well
as these 2 along with the PLLs they are clocked from must not be
disabled.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
clk: sunxi: Add support for bus clock gates on Allwinner A80 SoC

This adds the gate clocks for AHB/APB busses on the A80 SoC.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
clk: rockchip: change PLL setting for better clock jitter

dclk_vop0/1 is the source of HDMI TMDS clock in rk3288, usually we
use 594MHz for clock source of dclk_vop0/1.

HDMI CTS 7-9 require TMDS Clock jitter is lower than 0.25*Tbit:
TMDS clock(MHz)		CTS require jitter (ps)
	297		84.2
	148.5		168
	74.25		336
	27		1247

PLL BW and VCO frequency effects the jitter of PLL output clock,
clock jitter is better if BW is lower or VCO frequency is higher.

If PLL use default setting of RK3066_PLL_RATE( 594000000, 2, 198, 4),
the TMDS Clock jitter is higher than 250ps, which means we can't
pass the test when TMDS clock is 297MHz or 148.5MHz.

If we use RK3066_PLL_RATE_BWADJ(594000000, 1, 198, 8, 1),
the TMDS Clock jitter is about 60ps and we can pass all test case.

So we need this patch to make hdmi si test pass.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
clk: samsung: Document binding for Exynos4415 clock controller

This patch adds DT binding documentation for Exynos4415 SoC system
clock controllers.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
clk: samsung: exynos4415: Add clocks using common clock framework

This patch adds clock driver of Exynos4415 SoC based on Cortex-A9 using
common clock framework. The CMU (Clock Management Unit) of Exynos4415
controls PLLs(Phase Locked Loops) and generates system clocks for CPU,
busses and function clocks for individual IPs.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
clk: samsung: add support for 145xx and 1460x PLLs

PLL145xx is similar to PLL35xx and PLL1460x is almost similar
to PLL46xx with minor differences in bit positions. Hence,
reuse the functions defined for pll_35xx and pll_46xx to
support 145xx and 1460x PLLs respectively.

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Reviewed-by: Thomas Abraham <thomas.ab@samsung.com>
Tested-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
clk: samsung: Factor out the common code to clk.c

While adding clock support for Exynos5260, the infrastructure to
register multiple clock controllers was introduced. Factor out the
support for registering multiple clock controller from Exynos5260
clock code to common samsung clock code so that it can be used by
other Exynos SoC which have multiple clock controllers.

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Reviewed-by: Thomas Abraham <thomas.ab@samsung.com>
Tested-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
clk: samsung: Add fixed_factor_clocks field to struct exynos_cmu_info

Add the fields "fixed_factor_clks" and "nr_fixed_factor_clks" to
"struct exynos_cmu_info" to allow registering of fixed factor
clocks as well with exynos_cmu_register_one().

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Reviewed-by: Thomas Abraham <thomas.ab@samsung.com>
Tested-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
clk: samsung: add initial clock support for Exynos7 SoC

Add initial clock support for Exynos7 SoC which is required
to bring up platforms based on Exynos7.

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Reviewed-by: Thomas Abraham <thomas.ab@samsung.com>
Tested-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
clk: samsung: exynos7: add clocks for I2C block

Exynos7 supports 12 I2C channels, add the I2C gate clocks to
support them.

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
clk: samsung: exynos7: add clocks for MMC block

Exynos7 supports 3 MMC channels, add the MMC gate clocks to
support them.

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
clk: samsung: exynos7: add clocks for RTC block

Add clock support for the RTC block in Exynos7.

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
clk: samsung: exynos7: add gate clocks for WDT, TMU and PWM blocks

Add clock support for the watchdog timer, pwm timer and thermal
management unit IPs in Exynos7.

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
clk: samsung: exynos7: add gate clock for ADC block

Add clock support for the ADC interface in Exynos7.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>