- Skip over the testcases that call cbrtl on platforms where LDBL_PREC == 53
(arm, mips, powerpc). This fixes the build on these platforms, based on some
ad hoc tinderbox runs I did a while ago
- Skip cast the arguments to powl as long double so powl properly interprets
those arugments at compile-time when picking the type

Sponsored by: EMC / Isilon Storage Division
Do not do a cache invalidate on a PREREAD sync that is also a PREWRITE sync.
The PREWRITE handling does a writeback of any dirty cachelines, so there's
no danger of an eviction during the DMA corrupting the buffer.  There will
be an invalidate done during POSTREAD, so doing it before the read too is
wasted time.
Do the cache invalidate sequence from the outermost to innermost, required
for correct operation.

Submitted by:	Michal Meloun <meloun@miracle.cz>