Sending values to FPGA left sam and right not using
The values are for left sam and right are coming from ram
Only using even_odd & fwd_inv

  344   341   347 1 1     1     1 16705   341   344     0
  344   341   347 1 0   687   687 16705   341   344     0
  344   341   347 0 1   516   516 16705   341   344     0
  344   341   347 0 0   172   172 16705   341   344     0
All values are okay except 687 should be 688.