initial commit
downloaded to new top.vhd from wiki
replaced ALU with ALU in lab 2. All instructions in lab 3A works
Fix Instr(5 downto 0) for SLTU is "101001"
Done ADDI
implement HiLo registers
implement HiLo registers
test
fix bug in RegHiLo
modified .gitignore
connect RegHiLo signals
test
change RegHiLo to a 64 bits register
added 6 Shift Operations
added SLTI and SLTIU
fix RegHiLo
Fix RegHiLo
add ADDIU
Fix HiLo
Fix HiLo