vc4: Refuse to merge instructions involving 32-bit immediate loads.

An immediate load overwrites the mul and add operations, so you can't
merge with them.
vc4: Mark VPM read setup as impacting VPM reads, not writes.

Fixes assertion failures if we adjust scheduling priorities to emphasize
VPM reads more.
vc4: Skip raddr dependencies for 32-bit immediate loads.

These don't have raddr fields.
vc4: Populate the delay field better, and schedule high delay first.

This is a standard scheduling heuristic, and clearly helps.

total instructions in shared programs: 46418 -> 44467 (-4.20%)
instructions in affected programs:     42531 -> 40580 (-4.59%)
vc4: Do QPU scheduling across uniform loads.

This means another pass of reordering the uniform data store, but it lets
us pair up a lot more instructions.

total instructions in shared programs: 44639 -> 43176 (-3.28%)
instructions in affected programs:     36938 -> 35475 (-3.96%)
r600g: only init GS_VERT_ITEMSIZE on r600

On evergreen there are 4 regs, on r600/700 there is only one.

Don't initialise regs and trash someone elses state.

Not sure this fixes anything, but hey one less stupid.

Reviewed-By: Glenn Kennard <glenn.kennard@gmail.com>
Cc: "10.3 10.4" mesa-stable@lists.freedesktop.org
Signed-off-by: Dave Airlie <airlied@redhat.com>
clover: Use switch when creating kernel arguments.

This way we get a warning if an enum value is not handled.

v2: codestyle

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
gallium/aux: Avoid redefining MAX

* Can be redefined on some platforms through u_debug.h
gallium/target: Haiku softpipe

* Use print macro to fix warning on 64-bit systems
hgl: traverse add-on entries

* Allow using symlinks to add-ons when developing.
i965: Disable unlit-centroid workaround on Gen < 6.

Back to the original commit (8313f444) adding the workaround, we were
enabling it on gens <= 7, even though gens <= 5 can't do multisampling.

I cannot find documentation that says that Sandybridge needs this
workaround but in practice disabling it causes these piglit tests to
fail:

EXT_framebuffer_multisample/interpolation {2,4} centroid-deriv{,-disabled}

On Ironlake:

total instructions in shared programs: 4358478 -> 4349671 (-0.20%)
instructions in affected programs:     117680 -> 108873 (-7.48%)

A bunch of shaders in TF2, Portal 2, and L4D2 are cut by 25~30%.

Cc: "10.4" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
i965: Replace 'noann' debug flag with 'ann'.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
i965: Don't copy propagate constants from sources with saturate

We don't propagate the saturate bit and some instructions can't
saturate at all.  If the source has saturate set, just skip propagation.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Generalize fs_generator further

This removes all stage specific data from the generator, and lets us
create a generator for any stage.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Set shader name for generator from call site

fs_generator no longer knows what stage it's generating code for, so
we have to set the debug name of the shader from the call site.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Remove shader program argument and member from fs_generator

Now that the caller passes in the shader debug name, we don't need this
anymore.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Add SIMD8 URB write low-level IR instruction

This is all we need from the generator for SIMD8 vertex shaders.  This
opcode is just the send instruction, all the hard work will happen
in the visitor using LOAD_PAYLOAD.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Add new SIMD8 VS prog data flag

This flag signals that we have a SIMD8 VS shader so we can set up the
corresponding state accordingly.  This boils down to setting
the BDW+ SIMD8 enable bit in 3DSTATE_VS and making UBO and pull
constant buffers use dword pitch.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Consolidate code to get struct brw_sampler_prog_key_data

This chunk of code is repeated in a few places, and we're going to add
a MESA_SHADER_VERTEX case to it soon.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Prepare for using the ATTR register file in the fs backend

The scalar vertex shader will use the ATTR register file for vertex
attributes.  This patch adds support for the ATTR file to fs_visitor.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>