add netlist files; removed cyclic function in tx dma blocks
project file needed to build
remove swap channels from PL
Addition of AXI_FIFO blocks
addition of command verilog files
addition of Vivado constraint file
Support only builds on Windows machines
Update README.md
Activate uart0 in PS
Addition of export SDK directory
Enabled ethernet, Activate uart0 in PS
Addition of export SDK directory
Merge branch 'master' of https://github.com/silverbullettechnology/hdl-adi