powerpc: add CONFIG_SECURE_BOOT condition into fsl_secure_boot.h

This patch is for board config file not to add CONFIG_SECURE_BOOT
condition for include the asm/fsl_secure_boot.h.

Signed-off-by: Po Liu <Po.Liu@freescale.com>
powerpc:c29xpcie: make ifc timing parameter flexible

This patch re-config the NOR flash timing parameters which could make
the ifc timing more flexible for NOR flash.
The new parameters could fix the problem of hanging at "Flash:"
occasionally when booting the board.

Signed-off-by: Po Liu <Po.Liu@freescale.com>
powerpc/c29xpcie: modify DDR parameter to make DDR more stable

DDR parameters clk_adjust were changed. This can make the DDR
run more stable. The new value were gotten by the DDR testing
tool.

Signed-off-by: Po Liu <Po.Liu@freescale.com>
powerpc/mpc85xx:Make L2 cache type independent of CHASSIS2

CHASSIS2 architecture never defines type of L2 cache present in SoC.
 it is dependent upon the core present in the SoC.
 for example,
    - e6500 core has L2 cluster (Kibo)
    - e5500 core has Backside L2 Cache

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
powerpc/mpc85xx:Update processor defines for T1040

T1040 SoC has
    - DDR controller ver 5.0
    - 2 PLLs
    - 8 IFC Chip select
    - FMAN Muram 192K
    - No Srio
    - Sec controller ver 5.0
    - Max CPU update for its personalities

So, update the defines accordingly.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
powerpc/mpc85xx:Avoid fix clk groups for Cluster & HW accelerator

CHASSIS2 architecture never fix clock groups for Cluster and hardware
  accelerator like PME, FMA. These are SoC defined. SoC defines :-
    - NUM of PLLs present in the system
    - Clusters and their Clock group
    - hardware accelerator and their clock group
      if no clock group, then platform clock divider for FMAN, PME

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Corenet/p5040/SGMII:fix the problem for SGMII5/6

SGMII5/6 and SGMII7/8 are not on the same slot on P5040
according to the serdes protocol.
So it is not proper to organize SGMII5/6 and SGMII7/8
on one bus and SGMII5/6 can't work.
So a new bus SUPER_HYDRA_FM3_SGMII_MDIO is added for
SGMII5/6

Signed-off-by: Zhao Qiang <B45475@freescale.com>
SGMII:fix PHY addresses for QSGMII Riser Card working in SGMII mode

Fix PHY addresses for QSGMII Riser Card working in
SGMII mode on board P3041/P5020/P4080/P5040/B4860.

QSGMII Riser Card can work in SGMII mode, but
having the different PHY addresses.
So the following steps should be done:
	1. Confirm whether QSGMII Riser Card is used.
	2. If yes, set the proper PHY address.
Generally, the function is_qsgmii_riser_card() is
for step 1, and set_sgmii_phy() for step 2.

However, there are still some special situations,
take P5040 and B4860 as examples, the PHY addresses
need to be changed when serdes protocol is changed,
so it is necessary to confirm the protocol before
setting PHY addresses.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
powerpc: p1_p2_rdb_pc: Enable p1_p2_rdb_pc to boot from SD Card with SPL

Enable p1_p2_rdb_pc to start from eSDHC with SPL.

Signed-off-by: Ying Zhang <b40530@freescale.com>
powerpc : p1_p2_rdb_pc : Enable p1_p2_rdb_pc to start from eSPI with SPL

Enable p1_p2_rdb_pc to start from eSPI with SPL.

Signed-off-by: Ying Zhang <b40530@freescale.com>
powerpc: p1_p2_rdb_pc: add TPL for p1_p2_rdb_pc nand boot

Enable TPL for p1_p2_rdb_pc nand boot.

Signed-off-by: Ying Zhang <b40530@freescale.com>
board/bsc9131rdb: Update IFC timings for NAND flash

Current IFC timings for NAND flash are not able to support existing
K9F1G08U0B and new K9F1G08U0D flash.

so Update the timings to support both.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
powerpc/usb: Mention usb1 before usb2 inside default hwconfig string

For USB device-tree fix-up to work properly, its necessary to
mention USB1 options before that of USB2 inside default hwconfig
string

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
powerpc/t4240: updated rcw_cfg to align with default hardware configuration

Default configuration has been changed, the most important one is DDR
ref_clock which is changed from 66.67MHz to 133.33MHz. so the ratio need to
change from 24x to 12x to keep the DDR frequency. There are also some
other optimise to align with default configuration.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
powerpc/B4860: enable PBL tool for B4860

Use a default RCW of protocol 0x2A_0x98, and a PBI configure file which
uses CPC1 as 512KB SRAM, then PBL tool can be used on B4860 to build a
pbl boot image.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
powerpc/tool/pbl: fix pbl image compiling process

Previous process of compiling a PBL boot image is:
1: make <board_name_config>
2: make u-boot.pbl

for example:
make T4240QDS_SDCARD_config
make u-boot.pbl

Now the process is:
1: make <board_name>

for example:
make T4240QDS_SDCARD

Also, updated README.pblimage.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
powerpc: Fix CamelCase warnings in DDR related code

Some DDR related structures present in fsl_ddr_dimm_params.h, fsl_ddr_sdram.h, ddr_spd.h
has various parameters with embedded acronyms capitalized that trigger the CamelCase
warning in checkpatch.pl

Convert those variable names to smallcase naming convention and modify all files
which are using these structures with modified structures.

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
powerpc/t1040qds: Add T1040QDS board

T1040QDS is a high-performance computing evaluation, development and
test platform supporting the T1040 QorIQ Power Architecture™ processor.

 T1040QDS board Overview
 -----------------------
 - Four e5500 cores, each with a private 256 KB L2 cache
 - 256 KB shared L3 CoreNet platform cache (CPC)
 - Interconnect CoreNet platform
 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
   support
 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
 for the following functions:
    -  Packet parsing, classification, and distribution
    -  Queue management for scheduling, packet sequencing, and congestion
    	management
    -  Cryptography Acceleration
    - RegEx Pattern Matching Acceleration
    - IEEE Std 1588 support
    - Hardware buffer management for buffer allocation and deallocation
 - Ethernet interfaces
    - Integrated 8-port Gigabit Ethernet switch
    - Four 1 Gbps Ethernet controllers
 - SERDES Connections, 8 lanes supporting:
      — PCI Express: supporting Gen 1 and Gen 2;
      — SGMII
      — QSGMII
      — SATA 2.0
      — Aurora debug with dedicated connectors
 - DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and
   Interleaving
 -IFC/Local Bus
     - NAND flash: 8-bit, async, up to 2GB.
     - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
     - GASIC: Simple (minimal) target within Qixis FPGA
     - PromJET rapid memory download support
 - Ethernet
     - Two on-board RGMII 10/100/1G ethernet ports.
     - PHY #0 remains powered up during deep-sleep
 - QIXIS System Logic FPGA
 - Clocks
     - System and DDR clock (SYSCLK, “DDRCLK”)
     - SERDES clocks
 - Power Supplies
 - Video
     - DIU supports video at up to 1280x1024x32bpp
 - USB
     - Supports two USB 2.0 ports with integrated PHYs
     — Two type A ports with 5V@1.5A per port.
     — Second port can be converted to OTG mini-AB
 - SDHC
     - SDHC port connects directly to an adapter card slot, featuring:
     - Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC
     — Supporting eMMC memory devices
 - SPI
    -  On-board support of 3 different devices and sizes
 - Other IO
    - Two Serial ports
    - ProfiBus port
    - Four I2C ports

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: fix conflict in boards.cfg]
Acked-by-by: York Sun <yorksun@freescale.com>
powerpc/p1010rdb: remove unused cpld_show

Function cpld_show() was for debug and not called, so clean it.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
powerpc/eeprom: update MAX_NUM_PORTS to adapt non-256-bytes EEPROM

Some boards use System EEPROM with 128-bytes instead of 256-bytes.
Since we regard 256-bytes EEPROM as standard EEPROM with default
value for MAX_NUM_PORTS. For those non-256-bytes EEPROM, we can
redefine MAX_NUM_PORTS in board-specific file to override the
default MAX_NUM_PORTS.

This patch doesn't impact on previous existing boards.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>