fame1 queue compiles
fix build.scala
remove fame1 instance variables from Module.scala; disable memory enables with fire signals
merge with master
update nameIt in FameBackend
new io transform
fix fame1 transform for sequential mems
use regular register enables for mem seq read ports in CPP backend
fix io issues with referencechip
Merge branch 'master' of github.com:ucb-bar/chisel into fame1-transform
add fpga backend
Merge branch 'master' of github.com:ucb-bar/chisel