[zynq][spiflash] write enable before using the cr1 write routine

Change-Id: Id3dbffee2438bfca3208884b4a46cffeb79eccf2
[zynq][spiflash] wait a bit before rereading cr1 register

Change-Id: Ie791fb689f9c2bac9127ae27ac3a83274f67755a
[arch][arm] fix cache flush routines to pass proper address to pl310

-add another sync in a few of the pl310 routines
[arch][arm] add back the bottom bits in the returned address of arm_vtop()
[platform][zynq][gem] put the GEM driver in cached mode

Add appropriate flushing for the TX and RX path
[app][tests] beef up the cache benchmark tests a little bit
[dev][cache][pl310] r2+ versions of the pl310 do not require waiting for ops by PA
[app][inetsrv] add an echo server (port 7)
[lib][minip][tcp] add delayed ack, bump mss to 1460, add switch to disable checksum
[platform][zynq] extend gem test routine to take packet size

Change-Id: I44b3bb228a55858a2443a0057db9d97095d2870f
[lib][debug] spiff up hexdump() for non multiples of 16

-Only read the words once, and a word at a time.
-Properly handle truncating a non multiple of 16 line at
the next word boundary.

Change-Id: Ifbba0d921d343da903971027fcfff097c2c2207f
[arch][arm] turn on linker GC for big arm by default
[kernel] fix a warning that shows up with DEBUG=0
[app][tests] add new memory test

-Use the VMM to allocate a large chunk of uncached physical memory
-if no VMM, allocate from heap
-Do a simple own address test then a pattern and moving inversion test
[vm] Provisioning no-execute perm in the Arch MMU flags which can be used by x86-64 arch.
[vm] remove the static asserts for mmu_initial_mapping table

Side effect of making it 64bit okay.
[target][uzed] remove extraneous TIMER_CLOCK_FREQ #define