ENGR00296547-1 ARM: dts: imx6qdl-sabreauto-ecspi: use the gpio5_4 to enable the EIM_D18

The ECSPI needs the pin EIM_D18 which is controlled by the steering.
So we have to configurate the EIM_A24 to GPIO, and select the GPIO to LOW
status.

Signed-off-by: Huang Shijie <b32955@freescale.com>
ENGR00296547-2 ARM: dts: imx6qdl-sabreauto: add a new pinctrl for ECSPI1

The ECSPI1 needs the GPIO3_19 to select/de-select the SPI NOR chip.

This patch adds a new pinctrl for this GPIO, and select this pinctrl
when we enable the ECSPI1.

Signed-off-by: Huang Shijie <b32955@freescale.com>
mtd: gpmi: allocate a proper buffer for non ECC read/write

The @data_buffer_dma buffer is used for non ECC read/write.

Currently, the length of the buffer is PAGE_SIZE, but the NAND chip may
has 8K page or 16K page. So we have to extend it for the large page NAND
chips.

The gpmi_alloc_dma_buffer will be called twice. The first time is to
allocate a temporary buffer for scanning the NAND chip; The second time
is to allocate a buffer to store the real page content.

This patch allocates a buffer of PAGE_SIZE size for scanning the NAND
chip when gpmi_alloc_dma_buffer is called the first time, and allocates a
buffer of the real NAND page size for the second time gpmi_alloc_dma_buffer
is called.

Signed-off-by: Huang Shijie <shijie8@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Huang Shijie <b32955@freescale.com>
mtd: gpmi: add sanity check when mapping DMA for read_buf/write_buf

The buffer pointer passed from the upper layer may points to
a buffer in the stack or a buffer allocated by vmalloc, and etc..

This patch adds more sanity check to this buffer.
After this patch, if we meet a buffer which is allocated by vmalloc or
a buffer in the stack, we will use our own DMA buffer @data_buffer_dma
to do the DMA operations. If the buffer is not the cases above, we will
map it for DMA operations directly.

Signed-off-by: Huang Shijie <shijie8@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Huang Shijie <b32955@freescale.com>
mtd: mxc-nand: kill the NAND_MAX_PAGESIZE/NAND_MAX_OOBSIZE

We kill the NAND_MAX_PAGESIZE/NAND_MAX_OOBSIZE by the following way:
 1.) Before we call the nand_scan_ident, we allocate a temporary buffer
     whose size is PAGE_SIZE.
 2.) After we finish the nand_scan_ident, we have already getten the
     page size and oob size. We will allocate the right buffer size
     again.

Signed-off-by: Huang Shijie <shijie8@gmail.com>
Reviewed-by: Josh Triplett <josh@joshtriplett.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Huang Shijie <b32955@freescale.com>
mtd: denali: kill the NAND_MAX_PAGESIZE/NAND_MAX_OOBSIZE

This patch kills the NAND_MAX_PAGESIZE/NAND_MAX_OOBSIZE by the following
way:
 1.) change the @buf field of nand_buf{} from an array to a pointer.
     also remove the DENALI_BUF_SIZE macro.

 2.) Before we call the nand_scan_ident, we allocate a temporary buffer
     whose size is PAGE_SIZE.

 3.) After we finish the nand_scan_ident, we have already getten the
     page size and oob size. We will allocate the right buffer size
     again.

Signed-off-by: Huang Shijie <shijie8@gmail.com>
Reviewed-by: Josh Triplett <josh@joshtriplett.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Huang Shijie <b32955@freescale.com>
mtd: nand: kill the the NAND_MAX_PAGESIZE/NAND_MAX_OOBSIZE for nand_buffers{}

The patch converts the arrays to buffer pointers for nand_buffers{}.

The cafe_nand.c is the only NAND_OWN_BUFFERS user which allocates
nand_buffers{} itself.

This patch disables the DMA for nand_scan_ident, and restores the DMA
status after we finish the nand_scan_ident. This way, we can get page
size and OOB size and use them to allocate cafe->dmabuf.

Since the cafe_nand.c uses the NAND_ECC_HW_SYNDROME ECC mode, we do not
allocate the buffers for @ecccalc and @ecccode.

Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
mtd: nand: remove the NAND_MAX_PAGESIZE/NAND_MAX_OOBSIZE

There is no reference to these two macros now.
Just remove them.

Signed-off-by: Huang Shijie <shijie8@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Huang Shijie <b32955@freescale.com>
mtd: nand: add support for SanDisk SDTNRGAMA-008G

The datasheet does not tell us how to parse out the ID data,
so handle it as a full ID nand.

Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
mtd: nand: force NAND_CMD_READID onto 8-bit bus

The NAND command helpers tend to automatically shift the column address
for x16 bus devices, since most commands expect a word address, not a
byte address. The Read ID command, however, expects an 8-bit address
(i.e., 0x00, 0x20, or 0x40 should not be translated to 0x00, 0x10, or
0x20).

This fixes the column address for a few drivers which imitate the
nand_base defaults. Note that I don't touch sh_flctl.c, since it already
handles this problem slightly differently (note its comment "READID is
always performed using an 8-bit bus").

I have not tested this patch, as I only have x8 parts up for testing at
this point. Hopefully that can change soon...

Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-By: Pekon Gupta <pekon@ti.com>
Signed-off-by: Huang Shijie <b32955@freescale.com>
mtd: nand: don't use read_buf for 8-bit ONFI transfers

Use a repeated read_byte() instead of read_buf(), since for x16 buswidth
devices, we need to avoid the upper I/O[16:9] bits. See the following
commit for reference:

commit 05f7835975dad6b3b517f9e23415985e648fb875
Author: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Date:   Thu Dec 5 22:22:04 2013 +0100

    mtd: nand: don't use {read,write}_buf for 8-bit transfers

Now, I think that all barriers to probing ONFI on x16 devices are
removed, so remove the check from nand_flash_detect_onfi().

Tested on 8-bit ONFI NAND (Micron MT29F32G08CBADAWP).

Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-By: Pekon Gupta <pekon@ti.com>
Signed-off-by: Huang Shijie <b32955@freescale.com>
mtd: nand: fix misspelling in ONFI parameter field name

s/strenght/strength/

This field isn't used anywhere, so this rename is safe.

Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Huang Shijie <b32955@freescale.com>
ENGR00298274 hdmi: add zero check for hdmi audio pixel clock setting

Pixel clock may not initialized in the struct of fb_var_screeninfo
when video mode timing setting by user.
Add pixel clock zero check in hdmi audio clock update function
to avoid division by zero.

Signed-off-by: Sandor Yu <R01008@freescale.com>
ENGR00298524-1 ARM: dts: imx6sx: Add i.mx6sx soc dts support

Add i.MX6SX SOC and 17x17 arm2 board dts support, including
necessary modules info.

Signed-off-by: Anson Huang <b20788@freescale.com>
Acked-by: Jason Liu
ENGR00298524-2 ARM: imx: Add MSL support for i.mx6sx

It adds initial MSL support for i.mx6sx, including below features:

1. add cpu type check;
2. add system timer support;
3. add clock tree support;
4. add machine layer init support;

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
Acked-by: Jason Liu
ENGR00298524-3 ARM: imx: Enable imx6sx in defconfig

Enable imx6sx build in defconfig.

Signed-off-by: Anson Huang <b20788@freescale.com>
ENGR00298524-4 pinctrl: imx: add pinctrl driver for imx6sx

Add a pinctrl driver for i.MX6 SoloX based on pinctrl-imx core
driver.

Signed-off-by: Anson Huang <b20788@freescale.com>
ENGR00298524-5 ARM: dts: imx6sx: Add romcp module

Add ROMCP module and set it as syscon.

Signed-off-by: Anson Huang <b20788@freescale.com>
ENGR00298524-6 ARM: imx: enable suspend/resume for i.mx6sx

Enable suspend/resume feature for i.mx6sx 17x17 arm2 board,
for dsm mode, as we use dedicated ocram space for low
power function(start from 0x8f8000), but ROM code still
use previous ocram space(0x900000) for checking jump address,
so we need to enable ROMCP of data patch to workaround this
issue.

This patch only enables the suspend/resume function, will
add low power related operation such as DDR IO HZ mode setting
later, as there is still some necessary reference manual missing.

Signed-off-by: Anson Huang <b20788@freescale.com>
ENGR00298389 pcie: let rc can access mem of ep

- setup one new outbound memory region at rc side, used
to let imx6 pcie rc can access the memory of imx6 pcie ep
in imx6 pcie rc ep validation system.
- set the default address of the ddr memory to be 0x4000_0000

NOTE:
- default address 0x4000_0000 of ep side would be
accessed in this demo.
Test howto:
step1:
EP side:
1.1:
echo 0x40000000 > /sys/devices/soc0/soc.1/1ffc000.pcie/ep_bar0_addr

1.2:
memtool -32 0x40000000 4
E
Reading 0x4 count starting at address 0x40000000

0x40000000:  6FE9E9F6 7583FBB9 39EAEFEA FBDCFD78

step2:
RC side:
memtool -32 0x01000000=58D454DA
memtool -32 0x01000004=7332095B

step3:
EP side:
memtool -32 0x40000000 4
E
Reading 0x4 count starting at address 0x40000000

0x40000000:  58D454DA 7332095B 39EAEFEA FBDCFD78

Signed-off-by: Richard Zhu <r65037@freescale.com>