ARM: OMAP2+ / pm_debug: add support for wakeup_timer configuration

Add support for:
/sys/kernel/debug/pm_debug/wakeup_timer_seconds
/sys/kernel/debug/pm_debug/wakeup_timer_milliseconds

These allow for local interrupt source for testing purposes

NOTE: the timer is setup at suspend path, and the depth of the suspend
path *might* interfere with wakeup capability, for example, if very
short time period is provided, the timer may trigger before even the
kernel hits no_suspend_irq path, resulting in timer event being lost and
seemingly system in hung state.

Signed-off-by: Nishanth Menon <nm@ti.com>
ARM: OMAP5 / DRA7: PM: Update CPU context register offset

On OMAP5, RM_CPUi_CPUi_CONTEXT offset has changed. Update the code
so that same code works for OMAP4+ devices. DRA7 and OMAP5 have the same
context offset as well.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[rnayak@ti.com: for DRA7]
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: rebase, split/merge etc..]
Signed-off-by: Nishanth Menon <nm@ti.com>
ARM: OMAP5 / DRA7: PM: Set MPUSS-EMIF clock-domain static dependency

With EMIF clock-domain put under hardware supervised control, memory
corruption and untraceable crashes are observed on OMAP5. Further
investigation revealed that there is a weakness in the PRCM on this
specific dynamic depedency.

The recommendation is to set MPUSS static dependency towards EMIF
clock-domain to avoid issues. This recommendation holds good for DRA7
family of devices as well.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[rnayak@ti.com: DRA7]
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: conflict resolution, dra7]
Signed-off-by: Nishanth Menon <nm@ti.com>
ARM: OMAP5 / DRA7: PM / wakeupgen: Enables ES2 PM mode by default

Enables MPUSS ES2 power management mode using ES2_PM_MODE in
AMBA_IF_MODE register.

0x0: OMAP5 ES1 behavior, CPU cores would enter and exit OFF mode together.
     Broken! Fortunately, we do not support this anymore.
0x1: OMAP5 ES2, DRA7 behavior, CPU cores are allowed to enter/exit OFF mode
     independently.

This is one time settings thanks to always ON domain.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[nm@ti.com: minor conflict resolutions, consolidation for DRA7]
Signed-off-by: Nishanth Menon <nm@ti.com>
ARM: OMAP5 / DRA7: PM: Enable Mercury retention mode on CPUx powerdomains

In addition to the standard power-management technique, the OMAP5 / DRA7
MPU subsystem also employs an SR3-APG (mercury) power management
technology to reduce leakage.

It allows for full logic and memories retention on MPU_C0 and MPU_C1 and
is controlled by the PRCM_MPU. Only "Fast-mode" is supported on the
OMAP5 and DRA7 family of processors.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[nm@ti.com: minor consolidation]
Signed-off-by: Nishanth Menon <nm@ti.com>
ARM: OMAP5 / DRA7: PM: Avoid all SAR saves

Get rid of all assumptions about always having a sar base on *all*
OMAP4+ platforms. We dont need one on DRA7 and it is not necessary at
this point for OMAP5 either.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: Split and optimize]
Signed-off-by: Nishanth Menon <nm@ti.com>
ARM: OMAP5 / DRA7: PM: Provide a dummy startup function for CPU hotplug

Dont assume that all OMAP4+ code will be able to use OMAP4 hotplug
logic. On OMAP5, DRA7, we do not need this in place yet, also,
currently the CPU startup pointer is located in omap4_cpu_pm_info
instead of cpu_pm_ops.

So, isolate the function to hotplug_restart pointer in cpu_pm_ops
where it should have belonged, initalize them as per valid startup
pointers for OMAP4430/60 as in current logic, however provide
dummy_cpu_resume to be the startup location as well.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[nm@ti.com: split this out of original code and isolate it]
Signed-off-by: Nishanth Menon <nm@ti.com>
ARM: OMAP2+: powerdomain: pwrdm_for_each_clkdm iterate only valid clkdms

No need to invoke callback when the clkdm pointer is NULL.

Signed-off-by: Nishanth Menon <nm@ti.com>
ARM: OMAP2+: powerdomain: introduce logic for finding valid power domain

powerdomain configuration in OMAP is done using PWRSTCTRL register for
each power domain. However, PRCM lets us write any value we'd like to
the logic and power domain target states, however the SoC integration
tends to actually function only at a few discrete states. These valid
states are already in our powerdomains_xxx_data.c file.

So, provide a function to easily query valid low power state that the
power domain is allowed to go to.

Based on work originally done by Jean Pihet <j-pihet@ti.com>
https://patchwork.kernel.org/patch/1325091/ . There is no attempt to
create a new powerdomain solution here, except fixing issues seen
attempting invalid programming attempts. Future consolidation to the
generic powerdomain framework should consider this requirement as
well.

Similar solutions have been done in product kernels in the past such
as:
https://android.googlesource.com/kernel/omap.git/+blame/android-omap-panda-3.0/arch/arm/mach-omap2/pm44xx.c

Signed-off-by: Nishanth Menon <nm@ti.com>
ARM: OMAP4+: PM: Make logic state programmable

Move the logic state as different for each power domain. This allows us
to customize the deepest power state we should target over all for each
powerdomain in the follow on patches.

Signed-off-by: Nishanth Menon <nm@ti.com>
ARM: OMAP4+: PM: use only valid low power state for suspend

We are using power domain state as RET and logic state as OFF. This
state is OSWR. This may not always be supported on ALL power domains. In
fact, on certain power domains, this might result in a hang on certain
platforms. Instead, depend on powerdomain data to provide accurate
information about the supported powerdomain states and use the
appropriate function to query and use it as part of suspend path.

Signed-off-by: Nishanth Menon <nm@ti.com>
ARM: OMAP4+: PM: Use only valid low power state for CPU hotplug

Not all SoCs support OFF mode - for example DRA74/72. So, use valid
power state during CPU hotplug.

Signed-off-by: Nishanth Menon <nm@ti.com>
ARM: OMAP: DRA7: powerdomain data: fix powerdomain powerstate

DRA7 supports only CSWR for CPU, MPU power domains. Core power domain
supports upto INA.

Signed-off-by: Nishanth Menon <nm@ti.com>
ARM: OMAP5 / DRA7: Enable CPU RET on suspend

On OMAP5 / DRA7, prevent a CPU powerdomain OFF and resulting MPU OSWR
and instead attempt a CPU RET and side effect, MPU RET in suspend.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: update to do save_state only on DRA7]
Signed-off-by: Nishanth Menon <nm@ti.com>
ARM: DRA7: PM: cpuidle MPU CSWR support

Add DRA74/72 CPUIDLE support.

This patch adds MPUSS low power states in cpuidle.

        C1 - CPU0 WFI + CPU1 WFI + MPU ON
        C2 - CPU0 RET + CPU1 RET + MPU CSWR

Tested on DRA74/72-EVM for C1 and C2 states.

NOTE: DRA7 does not do voltage scaling as part of retention transition
and has Mercury which speeds up transition paths - Latency numbers are
based on measurements done by toggling GPIOs.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[ j-keerthy@ti.com rework on 3.14]
Signed-off-by: Keerthy <j-keerthy@ti.com>
[nm@ti.com: updates based on profiling]
Signed-off-by: Nishanth Menon <nm@ti.com>
ARM: OMAP5: Add hook in SoC initcalls to enable pm initialization

With consolidated code, now we can add the required hooks for
OMAP5 to enable power management.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[nm@ti.com: minor rebase updates]
Signed-off-by: Nishanth Menon <nm@ti.com>
ARM: DRA7: Add hook in SoC initcalls to enable pm initialization

With consolidated code, now we can add the required hooks for
DRA7 to enable power management.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: minor modifications]
Signed-off-by: Nishanth Menon <nm@ti.com>
cpufreq: suspend governors on system suspend/hibernate

[ Upstream commit 2f0aea9363609433b38ab13f0f86f38372668c68 ]

This patch adds cpufreq suspend/resume calls to dpm_{suspend|resume}() for
handling suspend/resume of cpufreq governors.

Lan Tianyu (Intel) & Jinhyuk Choi (Broadcom) found an issue where tunables
configuration for clusters/sockets with non-boot CPUs was getting lost after
suspend/resume, as we were notifying governors with CPUFREQ_GOV_POLICY_EXIT on
removal of the last cpu for that policy and so deallocating memory for tunables.
This is fixed by this patch as we don't allow any operation on governors after
device suspend and before device resume now.

We could have added these callbacks at dpm_{suspend|resume}_noirq() level but
the problem here is that most of the devices (i.e. devices with ->suspend()
callbacks) have already been suspended by now and so if drivers want to change
frequency before suspending, then it might not be possible for many platforms
(which depend on other peripherals like i2c, regulators, etc).

Reported-and-tested-by: Lan Tianyu <tianyu.lan@intel.com>
Reported-by: Jinhyuk Choi <jinchoi@broadcom.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
cpufreq: Implement cpufreq_generic_suspend()

[ Upstream commit e28867eab7c0a60cddf0cb59f9f6cbbd9561425d ]

Multiple platforms need to set CPU to a particular frequency before suspending
system. And so they need a common infrastructure which is provided by this
patch. Those platforms just need to initialize their ->suspend() pointers with
the generic routine.

Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Merge remote-tracking branch 'nmenon-platform/v3.14/devel/suspend-j6-o5-j6eco-pm-branch' into pm-ti-linux-3.14.y-next