N.B. INTERIM, DO NOT USE
Make delay line[s] d[DELAY_LENGTH] two samples longer, so a new sample coming down the cascade can by written (by the ISR) even if the
current convolutions (for two output samples) are not yet finished.
Looking at making d[] M+3 instead, so two new samples can be written (by I0++) without spoiling unfinished convolutions.
This because during the dual convolution-accumulate operation M+1 samples are needed, must not be overwritten.
Not yet implemented: filter cascade, SDRAM files for dwt outputs at different levels
I already wrote one

Mostly about making d[M] d{M+2], possibly d[M+3] so new samples coming
down the cascade can be written to d[] without disturbing an ongoing
convolution
Initial sequence design, about to change this, committing for look-back
About to rework for cascade

Consider use FP, also use all 6 Pregs