generated cmv_ram_fifo.vhd, began coding cmv_master.vhd, next steps: finish fsm, write testbench
testbench for cmv_master written, testing cmv_master at the moment
cmv_master tested, will now try to exchange camera_master_part.vhd with cmv_master.vhd
cmv_master_interface.vhd added, DataInxDI width changed to 80 instead of noOfchannels*channelWidth
qsys prepared for new cmv_master
compiles successfully with new cmv_master block, output on display is rubbish, have to look into dvi block
wrote dvi_master.vhd and generated ram_dvi_fifo.vhd, testbench for dvi_master.vhd is pending
dvi_master_interface added to QSYS, schematic adapted, does not compile. Next stepts, write testbench for dvi_master, add sequential process in dvi_master.vhd for ClkDvixCI
adjusted remapping and sync blocks for 16 channels
dvi_master_tb.vhd testbench file generated
cmv_master.vhd and cmv_master_tb.vhd and cmv_ram_fifo.vhd adjusted for 32bit in, 128bit out buffer
adjusted cmv_master and dvi_master interfaces in qsys, added current/next frame checker in cmv_master.vhd
currently working on dvi_master.vhd and according testbench, it does not compile -> problem because of multiple clockdomains?
changed cmv_master and dvi_master files, compiles without problem, but I cant upload the nios code anymore... wtf
design compiles and can be uploaded to nios2, output is still rubbish... be aware, that rstxrb signals in combinational processes could lead to failure, but this is not for sure
reviewed all address calculations etc., compiles and nios program can be uploaded, camera streams data to ram and from ram to monitor but 16*128 bits are always the same, will reduce clock speed tomorrow, clear signals need also to be better defined
integrated better BufClear routine, reset still doesnt work properly, will now focus on dvi_master and proper read out
changed fsm in dvi_master, monitores now the whole monitor, but still 16x the same part, will further investigate ram read-out (2048px vs 1920px resolution)