[stm32] SPI includes got jumbled for for DFF

DFF exists at bit 11 for f1, f2, f4 and l1, but the f0 and f3 have that bit as
CRC len and use CR2 for data size bits instead.  The merging of the F3 and F0
and attempts to put common data in common places broke the l1 code.

F3 and F0 SPI headers are still almost completely identical.
[stm32] Unify f0/f3 SPI and correct all makefiles

The common code wasn't being included in L1 builds, even though the headers now
included the correct definitions.

This combines the two f0 and f3 spi files, which previously differed only in
the number of spi peripherals defined.

Files were renamed to the full "l1f124" style, not because I like it, but
because it's the convention we have, so it's best to apply it rigourously.

Tested on L1 and F100 boards, compile tested only for others, but the examples
repository all compiles too.  (Though the lack of SPI examples for all
platforms was how this broke in the first place)
replaced placeholder __(en|dis)able_irq efm32_int functions with working ones
[timers] Fixed typo
- Bit shift should be 2, not 4 (see the datatsheet - TIMx_CMMR2 register)
[swo] Add/Update definitions necessary for SWO to work

ITM Stimulus ports need to be accessible with different sizes

The amount of data written out is determined by the size of the write.
Writing a full 32 bit value when you only need 8 for printf() style
substantially reduces the available bandwidth of the SWO

Note: this is an API change for doing 32bit writes.
Old:
    ITM_STIM[stimulus_port] = value
New:
    ITM_STIM32(stimulus_port) = value

This api is much more in common with some of the other registers that
behave this way.  As there's very little (if any) code already using
this API, it's a good time to fix it permanently.

Remove misleading ITM register definitions

ITM_SSPSR is the supported parallel trace size, in _bits_
ITM_CSPSR is in _bits_ as well.  There's really no advantage in even
having these sorts of definitions in libopencm3, as these settings are
normally controlled from the debugger side, not the target itself.

Lock and lock status register definitions were added, as per ARM:
  "For ARMv7-M, the component ID registers are required for the ROM table,
   and the CoreSight management lock access mechanism is defined for the
   DWT, ITM, FPB and TPIU blocks."
Fix the order of ADC injected channel list

According to RM0090, page 301, paragraph 11.13.12 Note. (For F4, for F1 and F3 is it in the corresponding manuals)

The JSQR are filled always ending at SQR4 ie for those lists we must set this list:

(A)       ->                               JSQ4 = A,
(A,B)     ->                     JSQ3 = A, JSQ4 = B,
(A,B,C)   ->           JSQ2 = A, JSQ3 = B, JSQ4 = C,
(A,B,C,D) -> JSQ1 = A, JSQ2 = B, JSQ3 = C, JSQ4 = D,

The readed values are in correct order, starting from JDR1:

(A)       -> JDR1 = A,
(A,B)     -> JDR1 = A, JDR2 = B,
(A,B,C)   -> JDR1 = A, JDR2 = B, JDR3 = C,
(A,B,C,D) -> JDR1 = A, JDR2 = B, JDR3 = C, JDR4 = D,
[stm32f3] Fix USART1 memory base address

Thanks to Uwe Bonnes on the mailing list.

Confirmed in the f37x and f30 ref manuals
[stm32] Add Factory Calibration values where available

Add memorymap entries for ST calibration data, the vref internal, and the temp
sensor at 30C and 110C for the parts that provide this data.

F1 and F2 do not appear to have this anywhere.