Removed PCB construction notes from .brd file, moved to README.
Added via-in-pad requirement to README.
Improved pin 1 silkscreen markings on several small packages. Updated PCB with modified footprints.
Moved R6 to not interfere with DDR2 socket. Had to replace a ground via.
Remove "do not manufacture" comments on PCB.
Regenerated netlist.
Resaved component mapping file (.cmp).
Changed mounting holes from plated to non-plated (since the drill and pad sizes were already equal).
Added zone to improve grounding to HSMC ground plane.
Filled PCB zones.
Generated Gerber and drill files.
Added README details about the two drill files.
Corrected incorrect imperial unit 50 Ohm trace width on bottom layer.
Made a bit more room between CLOCKGEN_OEB# and FE_I2C_SDA, to address DRC (due to rounding error?) in KiCAD -testing.
Corrected design rules to match newer layer stack: minimum trace of 6.5mil, minimum clearance, 5.0mil.
Altered 50 Ohm traces to new layer stack widths.
Fixed up some non-50 Ohm traces that needed widening due to new trace minimum widths.
Changed date on silkscreen.
Updated main board README with layer stack changes, affected materials, layer thicknesses, 50 Ohm trace widths.
Specified board thickness tolerance (before, I just said "approximately").
Clarified front and back layer types as "signal".
Updated all modules (footprints).
Re-read netlist.
Reconnected traces to pads.
Changed minimum Gerber line with to 6.5 mil.
Board and Gerbers for release.
Post-release commit of board file without filled zones.
Merge branch 'master' of github.com:jboone/daisho