Started new design for real.
Started simplified refactor
First iteration at solving rng mapping and signaling - removed many old files
Making progress on design - for module and channel components
Incremental additions
Added in configuration file parsing to Trie
Incremental additions
Compiles without error - added in samples files (untested)
TicToc Network creation successful
tictoc1 appears to have run
Up to TicToc 5 running
TicToc7 now running. Added in simtrace functionality
Fixed volatile readers - tictoc7 now running.
Tictoc10 now runnin - fixed gate and module array creation
Added numerical configuration path checks and ranges, fixed definition of around methods for volatile slot readers. TicToc14 running
Statistics functionality coded but untested
Statistics functionality now working
Split statistics base and implementation to fix bootstrapping issue
Tested out histogram autoranging - TicToc17 now running successfully
Fixed it so can specify differing initargs for module vectors by index. Also started wsn network