ARM: R9 is not safe to use for tcGPR.

Indirect tail-calls shouldn't use R9 for the branch destination, as
it's not reliably a call-clobbered register.

rdar://14793425

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188967 91177308-0d34-0410-b5e6-96231b3b80d8
FileCheck-ize tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188971 91177308-0d34-0410-b5e6-96231b3b80d8
Remove llvm-lit from the cmake install target.

Since it's an llvm-internal tool, we shouldn't install it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188976 91177308-0d34-0410-b5e6-96231b3b80d8
Teach LoopVectorize about address space sizes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188980 91177308-0d34-0410-b5e6-96231b3b80d8
[stackprotector] When finding the split point to splice off the end of a parentmbb into a successmbb, include any DBG_VALUE MI.

Fix for PR16954.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188987 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: respect tied 64-bit inlineasm operands when printing

The code for 'Q' and 'R' operand modifiers needs to look through tied
operands to discover the register class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188990 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: use TableGen patterns to select CMOV operations.

Back in the mists of time (2008), it seems TableGen couldn't handle the
patterns necessary to match ARM's CMOV node that we convert select operations
to, so we wrote a lot of fairly hairy C++ to do it for us.

TableGen can deal with it now: there were a few minor differences to CodeGen
(see tests), but nothing obviously worse that I could see, so we should
probably address anything that *does* come up in a localised manner.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188995 91177308-0d34-0410-b5e6-96231b3b80d8
Clean up the doxygen formatting of the comments on the strip* methods on
Value. These methods probably don't belong here, and I'm discussing
moving the lot of them to a better home, but for now I'm about to extend
their functionality and wanted to tidy them up first.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188997 91177308-0d34-0410-b5e6-96231b3b80d8
MemoryBuffer.cpp: Consider if PageSize were not 4096 in shouldUseMmap(). Follow-up to r188903.

The AllocationGranularity can be 65536 on Win32, even on Cygwin.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188998 91177308-0d34-0410-b5e6-96231b3b80d8
MemoryBufferTest.cpp: Tweak offset corresponding to the case that PageSize is greater than 8000.

PageSize, aka AllocationGranularity, is 65536 on Win32 (and Cygwin).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188999 91177308-0d34-0410-b5e6-96231b3b80d8
Add a new helper method to Value to strip in-bounds constant offsets of
pointers, but accumulate the offset into an APInt in the process of
stripping it.

This is a pretty handy thing to have, such as when trying to determine
if two pointers are at some constant relative offset. I'll be committing
a patch shortly to use it for exactly that purpose.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189000 91177308-0d34-0410-b5e6-96231b3b80d8
Suppress MemoryBufferTest.cpp on win32 for now. Investigating.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189001 91177308-0d34-0410-b5e6-96231b3b80d8
Fix ARM FastISel PIC function call.

The function call to external function should come with PLT relocation
type if the PIC relocation model is used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189002 91177308-0d34-0410-b5e6-96231b3b80d8
AVX-512: Added masked SHIFT commands, more encoding tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189005 91177308-0d34-0410-b5e6-96231b3b80d8
[ARM] Constrain some register classes in EmitAtomicBinary64 so that
we pass these tests with -verify-machineinstrs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189006 91177308-0d34-0410-b5e6-96231b3b80d8
Teach the SLP vectorizer the correct way to check for consecutive access
using GEPs. Previously, it used a number of different heuristics for
analyzing the GEPs. Several of these were conservatively correct, but
failed to fall back to SCEV even when SCEV might have given a reasonable
answer. One was simply incorrect in how it was formulated.

There was good code already to recursively evaluate the constant offsets
in GEPs, look through pointer casts, etc. I gathered this into a form
code like the SLP code can use in a previous commit, which allows all of
this code to become quite simple.

There is some performance (compile time) concern here at first glance as
we're directly attempting to walk both pointers constant GEP chains.
However, a couple of thoughts:

1) The very common cases where there is a dynamic pointer, and a second
   pointer at a constant offset (usually a stride) from it, this code
   will actually not do any unnecessary work.

2) InstCombine and other passes work very hard to collapse constant
   GEPs, so it will be rare that we iterate here for a long time.

That said, if there remain performance problems here, there are some
obvious things that can improve the situation immensely. Doing
a vectorizer-pass-wide memoizer for each individual layer of pointer
values, their base values, and the constant offset is likely to be able
to completely remove redundant work and strictly limit the scaling of
the work to scrape these GEPs. Since this optimization was not done on
the prior version (which would still benefit from it), I've not done it
here. But if folks have benchmarks that slow down it should be straight
forward for them to add.

I've added a test case, but I'm not really confident of the amount of
testing done for different access patterns, strides, and pointer
manipulation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189007 91177308-0d34-0410-b5e6-96231b3b80d8
Fix ARM vcvt encoding when the number of fractional bits is zero.

The instruction to convert between floating point and fixed point representations
takes an immediate operand for the number of fractional bits of the fixed point
value. ARMARM specifies that when that number of bits is zero, the assembler
should encode floating point/integer conversion instructions. 

This patch adds the necessary instruction aliases to achieve this behaviour.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189009 91177308-0d34-0410-b5e6-96231b3b80d8
Whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189020 91177308-0d34-0410-b5e6-96231b3b80d8
[Win32] mapped_file_region: Fix a bug in CreateFileMapping() that Size must contain Offset when Offset >= 65536.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189021 91177308-0d34-0410-b5e6-96231b3b80d8
[ARMv8] Add CodeGen support for VSEL.

This uses the ARMcmov pattern that Tim cleaned up in r188995.

Thanks to Simon Tatham for his floating point help!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189024 91177308-0d34-0410-b5e6-96231b3b80d8