clk: composite: .determine_rate support

This commit adds .determine_rate support to the composite clock. It will
use the .determine_rate callback from the rate component if available,
and fall back on the mux component otherwise. This allows composite
clocks to enjoy the benefits of automatic clock reparenting.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
clk: sunxi: factors: fix off-by-one masks

The previous code would generate one bit too long masks, and was
needlessly complicated. This patch replaces it by simpler code that can
generate the masks correctly.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
clk: sunxi: factors: clear variables before using them

Random bits may get into our factors if we don't clear n, k, m and p.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
clk: sunxi: protect core clocks from accidental shutdown

Some important clocks may get disabled as a side effect of another clock
being disabled, because they have no consumers. This patch implements a
mechanism so those clocks can be claimed by the driver and therefore
remain enabled at all times.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
drivers: clk: sunxi: Fix memory leakage in clk-sunxi.c

Fix a possible memory leak in sun4i_osc_clk_setup().
Moved clock-frequency check to save superfluous allocation.

Signed-off-by: Victor N. Ramos Mello <victornrm@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
ARM: tegra114: add missing clocks to binding

commit 992bb598f690542a2f539fd12a42b960b7692025 forgot to move dfll_soc and
dfll_ref to include/dt-bindings/clock/tegra114-car.h. Add them again in this
patch as TEGRA114_CLK_DFLL_SOC and TEGRA114_CLK_DFLL_REF.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
clk: tegra: replace enum tegra114_clk by binding header

As the clock IDs are now specified in a header file, we can use those
definitions instead of maintaining an internal enum.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
clk: tegra: Correct sbc mux width & parent

Tegra114 sbc1-sbc6 have more possible parent clocks than Tegra30.
So correct the parents and mux width for them.

Signed-off-by: Mark Zhang <markz@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
clk: tegra: Fix vde/2d/3d clock src offset

In Tegra114, vde/gr_2d/gr_3d have 3 bits for clock source selection.
So change the clock init macro for these clocks from
"TEGRA_INIT_DATA_INT" to "TEGRA_INIT_DATA_INT8".

Besides, no one uses "TEGRA_INIT_DATA_INT" after this change, so
remove this macro.

Signed-off-by: Mark Zhang <markz@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
clk: tegra: Set the clock parent of gr2d/gr3d to pll_c2

pll_m will be the parent of gr2d/gr3d if we don't do this.
And because pll_m runs at a high rate so gr2d/gr3d will be
unstable. So change the parent of them to pll_c2.

Signed-off-by: Mark Zhang <markz@nvidia.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
clk: tegra: add TEGRA_DIVIDER_ROUND_UP for periph clks

Perform upwards rounding when calculating dividers for periph clks on Tegra30
and Tegra114.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
clk: tegra: Set the clk parent of host1x to pll_p

The power-on default parent for this clock is pll_m, which turns out to
be wrong. Previously, bootloader reparented this clock.  We'll do it in
the kernel as well, so that there's one less thing that we depend on
bootloader to initialize.

Signed-off-by: Andrew Chew <achew@nvidia.com>
Signed-off-by: Mark Zhang <markz@nvidia.com>
clk: tegra: PLLE spread spectrum control

Add spread spectrum control for PLLE in Tegra114.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
clk: tegra114: Rename gr_2d/gr_3d to gr2d/gr3d

These clocks were named gr2d and gr3d on Tegra20 and Tegra30, so use the
same names on Tegra114 for consistency.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra30: add missing CLK IDs

The Tegra30 clock bindings lack few IDs for audio and clk_out muxes.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
clk: tegra: Fix clock rate computation

The PLL output frequency is multiplied during the P-divider computation,
so it needs to be divided by the P-divider again before returning.

This fixes an issue where clk_round_rate() would return the multiplied
frequency instead of the real one after the P-divider.

Signed-off-by: Thierry Reding <treding@nvidia.com>
clk: tegra: simplify periph clock data

This patch determines the register bank for clock enable/disable and reset
based on the clock ID instead of hardcoding it in the tables describing the
clocks. This results in less data to be maintained in the tables, making the
code easier to understand. The full benefit of the change will be realized once
also other clocktypes will be table based.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
clk: tegra: common periph_clk_enb_refcnt and clks

This patch makes periph_clk_enb_refcnt a global array, dynamically allocated
at boottime. It simplifies the macros somewhat and allows clocks common to
several Tegra SoCs to be defined in a separate files. Also the clks array
becomes global and dynamically allocated which allows the DT registration to
be moved to a generic funcion.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
clk: tegra: Add TEGRA_PERIPH_NO_DIV flag

This flag indicates the peripheral clock does not have a divider. It will
simplify the initialization tables and avoids some very similar code.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
clk: tegra: move some PLLC and PLLXC init to clk-pll.c

VCO min clipping, dynamic ramp setup and IDDQ init can be done in the
respective PLL clk_register functions if the parent is already registered.
This is done for other some PLLs already.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>