Move *coma/ to *cdma/.
Rename "COMA" to "CDMA".

The explanation was published in [1]:

There are two families of models, referred to as "COMA" and "ZLCOMA" in
MGSim's source code. Their use of the acronym "COMA" is due to
historical ties between this research and related work on Cache-Only
Memory Architectures in the 1990's.  In the original COMA vision from
the 1990's, a protocol between the memories ensures that all addresses
are present somewhere in the network. The corresponding key feature is
that the blocks of data corresponding to the most frequently used
addresses can be migrated to the part of the system where they are most
frequently used. Because of this feature, each memory in the system is
also called attraction memory (AM).  However, the memory architecture
modeled in MGSim's library has diverged from the original COMA
concept. The reason is that it is difficult to fit the entire DRAM
storage of a system onto a single chip, and off-chip COMA caches and
directories are difficult to manage at the latency and bandwidth scales
required by on-chip parallelism. Instead, the [CDMA model in MGSim]
still uses static partitioning of the address space across memory banks,
but uses a distributed network of caches on chip with a similar
attraction property as a COMA: cache lines fetched once in the cache
network tend to stay within the network, so as to avoid off-chip memory
accesses as much as possible. Moreover, a cache miss in one part of the
network is resolved by fetching data from another part if it can be
found, instead of fetching from external memory. As with a COMA, on-chip
directories remember which addresses can be currently found within the
on-chip cache network.  Because of this difference with COMAs, the
memory architecture modeled in MGSim would be best described as a cache
diffusion memory architecture (CDMA), based on attraction caches (AC)
and a cache diffusion network (CDN).

[1] Mike Lankamp, Raphael Poss, Qiang Yang, Jian Fu, Irfan Uddin, and
Chris R. Jesshope. MGSim---simulation tools for multi-core processor
architectures. Technical Report arXiv:1302.1390v1 [cs.AR], University of
Amsterdam, February 2013. URL http://arxiv.org/abs/1302.1390
Rename: Processor -> DRISC
Move arch/proc/ to arch/drisc/.
Separate DRISC::Connect() from DRISC::Initialize() for FPU, Net and IOBus links.
Remove unused MGSystem::m_procbusmapping.