i2c-sc18is60x: fix error propagation

Fix return value in sc18is60x_master_xfer so all I2C transfer
errors get returned to user space.

Signed-off-by: Guillaume Tucker <guillaume.tucker@plasticlogic.com>
i2c-sc18is60x: fix log messages

Add missing line feeds in dev_* log messages.

Signed-off-by: Guillaume Tucker <guillaume.tucker@plasticlogic.com>
drivers/i2c/busses: add i2c-s1d135x1 SPI-I2C bridge driver

Add a new I2C bus driver using the SPI-I2C bridge feature
provided by the S1D135x1 Epson EPD controller.  This relies on
the main S1D135x1 driver to initialise the controller and
populate the API functions for the SPI-I2C driver via the
s1d135x1_spi structure, defined in include/linux/modelffb.h.

It polls the status register using SPI transactions to wait for
the completion of I2C messages.  This could be improved by
sharing the interrupt from the main S1S135x1 driver, which would
increase the I2C throughput but also the code complexity.

Signed-off-by: Guillaume Tucker <guillaume.tucker@plasticlogic.com>
S1D135x1: implement SPI-I2C bridge driver interface

Populate the s1d135x1_spi and move the pl_hardware initialisation
only after the SPI-I2C bridge driver is initialised as it may
need it if enabled.

Use i2c-5 when the SPI-I2C bridge driver is enabled, or i2c-3
otherwise.  This still needs to be moved to the platform data.

Signed-off-by: Guillaume Tucker <guillaume.tucker@plasticlogic.com>
S1D135x1: set the I2C clock divider register

When SPI-I2C is enabled, set the I2C divider value in the
register as provided by the platform data.

* add modelffb_platform_data.i2c_clk_divider
* add address of I2C clock divider register
* add call to write register value in chip_init.

Signed-off-by: Guillaume Tucker <guillaume.tucker@plasticlogic.com>
am335xevm: add definitions for i2c-s1d135x1 driver

When the S1D135x1 SPI-I2C bus driver is enabled, register it
as a platform device to create the i2c-5 bus.

Also set the value of the I2C clock divider via the
modelffb_platform_data structure.  The value of 4 should result
in 100kHz SPI clock.

Signed-off-by: Guillaume Tucker <guillaume.tucker@plasticlogic.com>
pl_hardware: remove power and reset GPIOs

Remove Epson S1D135x1 reset and power GPIO definitions as they
now need to be controlled by the modelffb driver.  They have
nothing to do with the PL hardware.

Signed-off-by: Guillaume Tucker <guillaume.tucker@plasticlogic.com>
S1D135x1: add optional GPIOs for reset and power enable

Add basic support for the `reset' and `pwr_en' GPIOs as
configured via the platform data.

Some platforms have dedicated pins to reset the controller and to
enable the power of the display electronics.  They need to be
driven high in order to power it and not hold the controller in
reset.

Signed-off-by: Guillaume Tucker <guillaume.tucker@plasticlogic.com>
am335xevm: add `pwr_en' and `reset' GPIOs for S1D135x1

Signed-off-by: Guillaume Tucker <guillaume.tucker@plasticlogic.com>
am335xevm: change S1D135x1 SPI clock frequency

Change the S1D135x1 SPI clock frequency depending on the target
PL hardware platform:

* Z5: 24MHz -> 12MHz to allow longer cable
* Z6-Z7: 12MHz -> 24MHz for standard short cable

Signed-off-by: Guillaume Tucker <guillaume.tucker@plasticlogic.com>
S1D135x1: add left and right border parameters

Add parinfo->left_border and ->right_border which represent the
number of source lines on either side of the display that are not
part of the active area.  The framebuffer is then created to
match the active area, and the pixels outside this are ignored by
the software.

This is currently not fully configurable from user-side but is
hard-coded for PL panel types.  For Type16, the left border is
set to 80.  For Type17, the right border is set to 7.

Signed-off-by: Guillaume Tucker <guillaume.tucker@plasticlogic.com>
am335xevm: ignore standard EEPROMs with PL hardware

When CONFIG_MODELF_PL_HARDWARE is enabled, ignore the standard
cape and daughter board EEPROMs as they are not used on PL
expansion boards.

Signed-off-by: Guillaume Tucker <guillaume.tucker@plasticlogic.com>
S1D135x1: add SPI clock frequency option via sysfs

Add `spi_freq_hz' option to the `setop' command on the `control'
sysfs interface.  This is then used to override the default SPI
frequency set on the platform, in HZ.  All SPI transactions in
the driver then use this frequency.  Setting it to 0 reverts to
the platform default value.

This is stored in modelffb_par.opt.spi_freq_hz.

+ simplify syntax when sending only one SPI packet

Signed-off-by: Guillaume Tucker <guillaume.tucker@plasticlogic.com>