Hi Victor,

The Cache Line size is 64 bytes. The mPIPE alignment requirements is then 2 cachelines.

It would likely help all architectures to at least align to cachelines for the Packet structure.

Regards,
-Ken

From: Victor Julien [mailto:notifications@github.com]
Sent: Monday, July 15, 2013 11:47 AM
To: inliniac/suricata
Cc: Kenneth Steele
Subject: Re: [suricata] Add TILE-Gx mPIPE packet processing support. (#431)


In src/decode.h:

> @@ -494,7 +499,13 @@ enum PktSrcEnum {

>  #ifdef __SC_CUDA_SUPPORT__

>      CudaPacketVars cuda_pkt_vars;

>  #endif

> -} Packet;

> +}

> +#ifdef HAVE_MPIPE

> +/* mPIPE requires packet buffers to be aligned to 128 byte

> +   boundaries. */

> +  __attribute__((aligned(128)))

We have a CLS define now, the L1 cache line size. Is this by any chance the Tilera CLS? If so, we might want to try just using the CLS here, might be beneficial on x86 as well.

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Reply to this email directly or view it on GitHub<https://github.com/inliniac/suricata/pull/431/files#r5192783>.