STM32: moved timer_ic_set_polarity from timer_common_all to
f1/timer.
Added timer_ic_set_polarity to timer_common_f24 with
the enum tim_ic_pol now including trigger on both edges.
Changed timer_slave_set_polarity to use enum tim_et_pol
rather than tim_ic_pol.

In response to suggestion of stinkydiver73 on 24 March that
timers in all families have an option for triggers on both
edges, except F1.
[stm32] usart6 for F2/F4
[stm32] update doxy for usart_set_baudrate
lm4f: Properly set PLL divisor

rcc_set_pll_divisor() would take the number we wanted to divide the 400MHz
clock and put it directly in the RCC2 register. This caused the clock to always
be one speed tier slower than expected. The value of the divisor must be
decremented by 1, so a divisor of 5 will be written as 4 in the RCC2.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
lm4f: Fix include guard in nvic.h

The lm4f/nvic.h include guard was wrongfully named LIBOPENCM3_LM3S_NVIC_H.
This caused the lm3s/nvic.h include a few lines down to not be compiled.
Rename the inlcude guard to the more appropriate LIBOPENCM3_LM4F_NVIC_H.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>