CHROMIUM: add "SPINLOCKUP" trigger to lkdtm

Allow spinlock lockup testing via the lkdtm interface.

BUG=chromium:215167
TEST=`echo SPINLOCKUP >/sys/kernel/debug/provoke-crash/DIRECT`

Change-Id: I93dd5d3750cd1219831ffb3076ea15ecf51a0aca
Signed-off-by: Kees Cook <keescook@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/59688
Reviewed-by: Luigi Semenzato <semenzato@chromium.org>
ARM: b.L: core switcher code

This is the core code implementing big.LITTLE switcher functionality.
Rational for this code is available here:

http://lwn.net/Articles/481055/

The main entry point for a switch request is:

void bL_switch_request(unsigned int cpu, unsigned int new_cluster_id)

If the calling CPU is not the wanted one, this wrapper takes care of
sending the request to the appropriate CPU with schedule_work_on().
In the future, some switching related tasks which do not require a
strict CPU affinity might be moved here though.

At the moment the core switch operation is handled by bL_switch_to()
which must be called on the CPU for which a switch is requested.

What this code does:

  * Return early if the current cluster is the wanted one.

  * Close the gate in the kernel entry vector for both the inbound
    and outbound CPUs.

  * Wake up the inbound CPU so it can perform its reset sequence in
    parallel up to the kernel entry vector gate.

  * Migrate all interrupts in the GIC targeting the outbound CPU
    interface to the inbound CPU interface, including SGIs. This is
    performed by gic_migrate_target() in arch/arm/common/gic.c.

  * Call cpu_pm_enter() which takes care of flushing the VFP state to
    RAM and save the CPU interface config from the GIC to RAM.

  * Call cpu_suspend() which saves the CPU state (general purpose
    registers, page table address) onto the stack and store the
    resulting stack pointer in an array indexed by processor number,
    then call the provided shutdown function.  This happens in
    arch/arm/kernel/sleep.S.

At this point, the provided shutdown function executed by the outbound
CPU ungates the inbound CPU. Therefore the inbound CPU:

  * Picks up the saved stack pointer in the array indexed by
    processor number above. At the moment the corresponding code in
    arch/arm/kernel/sleep.S only looks at the CPU number field in the
    MPIDR so the current code works unmodified even if the new CPU
    comes from a different cluster.

  * The MMU and caches are re-enabled using the saved state on the
    provided stack, just like if this was a resume operation from a
    suspended state.

  * Then cpu_suspend() returns, although this is on the inbound CPU
    rather than the outbound CPU which called it initially.

  * The function cpu_pm_exit() is called which effect is to restore the
    CPU interface state in the GIC using the state previously saved by
    the outbound CPU.

  * Exit of bL_switch_to() to resume normal kernel execution on the
    new CPU.

However, the outbound CPU is potentially still running in parallel while
the inbound CPU is resuming normal kernel execution, hence we need
per CPU stack isolation to execute bL_do_switch().  After the outbound
CPU has ungated the inbound CPU, it calls bL_cpu_power_down() to:

  * Clean its L1 cache.

  * If it is the last CPU still alive in its cluster (last man standing),
    it also cleans its L2 cache and disables cache snooping from the other
    cluster.

Code called from bL_do_switch() might end up referencing 'current' for
some reasons.  However, 'current' is derived from the stack pointer.
With any arbitrary stack, the returned value for 'current' and any
dereferenced values through it are just random garbage which may lead to
segmentation faults.

The active page table during the execution of bL_do_switch() is also a
problem.  There is no guarantee that the inbound CPU won't destroy the
corresponding task which would free the attached page table while the
outbound CPU is still running and relying on it.

To solve both issues, we borrow some of the task space belonging to
the init/idle task which, by its nature, is lightly used and therefore
is unlikely to clash with our usage.  The init task is also never going
away.

Signed-off-by: Nicolas Pitre <nico@linaro.org>
(cherry picked from commit bdabef6198dee2a084e0663532b3729402d14103)
(cherry-picked from: git://git.linaro.org/people/nico/linux.git)

BUG=chrome-os-partner:19820
TEST=Booted peach.  Currently a no-op since IKS is not enabled.

Change-Id: I95cba4539ecd60ba1e4b2c9246f0416205d4e046
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/59030
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Andrew Bresticker <abrestic@chromium.org>
ARM: bL_switcher: add clockevent save/restore support

Per-CPU timers that are shutdown when a CPU is switched over must be disabled
upon switching and reprogrammed on the inbound CPU by relying on the
clock events management API. save/restore sequence is executed with irqs
disabled as mandated by the clock events API.

The next_event is an absolute time, hence, when the inbound CPU resumes,
if the timer has expired the min delta is forced into the tick device to
fire after few cycles.

This patch adds switching support for clock events that are per-CPU and
have to be migrated when a switch takes place; the cpumask of the clock
event device is checked against the cpumask of the current cpu, and if
they match, the clockevent device mode is saved and it is put in
shutdown mode. Resume code reprogrammes the tick device accordingly.

Tested on A15/A7 fast models and architected timers.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Nicolas Pitre <nico@linaro.org>
(cherry picked from commit 729e17e246e9f5c4be105f42291a57d4bdd85f68)
(cherry-picked from: git://git.linaro.org/people/nico/linux.git)

BUG=chrome-os-partner:19820
TEST=Booted peach.  Currently a no-op since IKS is not enabled.

Change-Id: I1ee0d3d32147e72dc7fb5d9441f4a500d8def628
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/59031
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Andrew Bresticker <abrestic@chromium.org>
ARM: bL_switcher: move to dedicated threads rather than workqueues

The workqueues are problematic as they may be contended.
They can't be scheduled with top priority either.  Also the optimization
in bL_switch_request() to skip the workqueue entirely when the target CPU
and the calling CPU were the same didn't allow for bL_switch_request() to
be called from atomic context, as might be the case for some cpufreq
drivers.

Let's move to dedicated kthreads instead.

Signed-off-by: Nicolas Pitre <nico@linaro.org>
(cherry picked from commit 9ab74b984780dc8c8b0a62011552abbfd99b3c86)
(cherry-picked from: git://git.linaro.org/people/nico/linux.git)

BUG=chrome-os-partner:19820
TEST=Booted peach.  Currently a no-op since IKS is not enabled.

Change-Id: I9af6378811044edd2dd389a78642cf82b75414f7
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/59032
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Andrew Bresticker <abrestic@chromium.org>
ARM: bL_switcher: simplify stack isolation

We now have a dedicated thread for each logical CPU.  That's plenty
of stack space for our needs.

Signed-off-by: Nicolas Pitre <nico@linaro.org>
(cherry picked from commit 0d7c439d50f69c2f1f30d644265fdbb93e0798ec)
(cherry-picked from: git://git.linaro.org/people/nico/linux.git)

BUG=chrome-os-partner:19820
TEST=Booted peach.  Currently a no-op since IKS is not enabled.

Change-Id: I1556c6b9114380894ba2ff5e9a5a72dd59eab41b
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/59033
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Andrew Bresticker <abrestic@chromium.org>
ARM: bL_switcher: hot-unplug half of the available CPUs

With an MP kernel, all the CPUs are initially available.  The switcher
model always uses half of them at any time.  Let's remove half of the
available CPUs and make sure we still have a working switcher
configuration.

Signed-off-by: Nicolas Pitre <nico@linaro.org>
(cherry picked from commit 0ed7390292d925cfef71d29134451370c36b4112)
(cherry-picked from: git://git.linaro.org/people/nico/linux.git)

BUG=chrome-os-partner:19820
TEST=Booted peach.  Currently a no-op since IKS is not enabled.

Change-Id: I1ec43605fbf954ab3692962e1f93c91db6a4aba2
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
[abrestic: fixed style errors]
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/59034
ARM: bL_switcher: do not hardcode GIC IDs in the code

Currently, GIC IDs are hardcoded making the code dependent on the x4 b.L
configuration.  Let's allow for GIC IDs to be discovered upon switcher
initialization to support other b.L configurations such as the x1 one.

Signed-off-by: Nicolas Pitre <nico@linaro.org>
(cherry picked from commit eb3525e4e0279291d89546a1d8c240079943b8b2)
(cherry-picked from: git://git.linaro.org/people/nico/linux.git)

BUG=chrome-os-partner:19820
TEST=Booted peach.  Currently a no-op since IKS is not enabled.

Change-Id: I13b63d147baf2982a0a9ae2c9621c9c0a8f490b1
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
[abrestic: fixed style errors]
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/59035
ARM: bL_switcher: ability to enable and disable the switcher via sysfs

The /sys/kernel/bL_switcher/enable file allows to enable or disable
the switcher by writing 1 or 0 to it respectively.  It is still enabled
by default on boot.

Signed-off-by: Nicolas Pitre <nico@linaro.org>
(cherry picked from commit 9b7beeac2a8f6f2629625e0766dbbd8582e43bd7)
(cherry-picked from: git://git.linaro.org/people/nico/linux.git)

BUG=chrome-os-partner:19820
TEST=Can disable/enable IKS at runtime nce IKS support is added and enabled.

Change-Id: I2f6374271a170c6e3085e89e20260c28e7dd23ce
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>#
[abrestic: fixed style errors]
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/59039
ARM: bL_switcher: add kernel cmdline param to disable the switcher on boot

By adding no_bL_switcher to the kernel cmdline string, the switcher
won't be activated automatically at boot time.  It is still possible
to activate it later with:

	echo 1 > /sys/kernel/bL_switcher/active

Signed-off-by: Nicolas Pitre <nico@linaro.org>
(cherry picked from commit 345909633144390112598ed9a8ba05ef76c6c0f9)
(cherry-picked from: git://git.linaro.org/people/nico/linux.git)

BUG=chrome-os-partner:19820
TEST=Adding "no_bL_switcher" to the command line disables IKS once IKS
support is added and enabled.

Change-Id: I5ad5a9762c71ecdd141ef5eee7ff1923ce7bb206
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/59040
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Andrew Bresticker <abrestic@chromium.org>
ARM: bL_switcher: veto CPU hotplug requests when the switcher is active

Trying to support both the switcher and CPU hotplug at the same time
is quickly becoming very complex due to ambiguous semantics.  So let's
simply veto any hotplug requests when the switcher is active for now.

This restriction might be loosened eventually.

Signed-off-by: Nicolas Pitre <nico@linaro.org>
(cherry picked from commit 57ec6e48712f52c31accb7deca46899032766948)
(cherry-picked from: git://git.linaro.org/people/nico/linux.git)

BUG=chrome-os-partner:19820
TEST=Booted peach

Change-Id: Ib281e8ba6027d2d2b3389d10687086925a2d6a91
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
[abrestic: fixed style errors]
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/59041
ARM: bL_switcher: add a simple /dev user interface for debugging purposes

Only the basic to aid debugging.

Usage:

	echo <cpuid>,<clusterid> > /dev/b.L_switcher

where <cpuid> is between 0 and 3, and <clusterid> is 0 for the
A15 cluster and 1 for the A7 cluster.

Signed-off-by: nicolas Pitre <nico@linaro.org>
(cherry picked from commit fb57f198a209840d4e4653a5883d0f184a1a77ee)
(cherry-picked from: git://git.linaro.org/people/nico/linux.git)

BUG=chrome-os-partner:19820
TEST=Can use /dev/b.L_switcher to request switches once IKS support is
added and enabled.

Change-Id: I7bbbd9072f681a50144f7fc81daacb0de9cbfbbe
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
[abrestic: fixed style errors]
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/59051
ARM: bL_switcher: synchronize the outbound with the inbound

Let's wait for the inbound to come up and snoop some of the outbound
cache. That should be a bit more efficient than going down right away.
Monitoring the CCI event counters could be a better approach
eventually.

Signed-off-by: Nicolas Pitre <nico@linaro.org>
(cherry picked from commit 8e9c2d29bf6fee7a99db920c8a08aa691c2973d3)
(cherry-picked from: git://git.linaro.org/people/nico/linux.git)

BUG=chrome-os-partner:19820
TEST=Booted peach

Change-Id: I10f2c0343bc9ad6affff0844052f5728761fe32e
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/59042
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Andrew Bresticker <abrestic@chromium.org>
ARM: GIC: function to retrieve the physical address of the SGIR

In order to have early assembly code signal other CPUs in the system,
we need to get the physical address for the SGIR register used to
send IPIs.  Because the register will be used with a precomputed CPU
interface ID number, there is no need for any locking in the assembly
code where this register is written to.

Signed-off-by: Nicolas Pitre <nico@linaro.org>
(cherry-picked from commit df321c43e3c3ed44d2434fd12d378736a82152d5)
(cherry-picked from: git://git.linaro.org/people/nico/linux.git)

BUG=chrome-os-partner:19820
TEST=Booted peach

Change-Id: I9c0260a9285f7e99fbe23540afb48f6049d4a29f
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
[abrestic: fixed style errors]
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/59036
ARM: GIC: interface to send a SGI directly

The regular gic_raise_softirq() takes as input a CPU mask which is not
adequate when we need to send an IPI to a CPU which is not represented
in the kernel to GIC mapping.  That is the case with the b.L switcher
when GIC migration to the inbound CPU has not yet occurred.

Signed-off-by: Nicolas Pitre <nico@linaro.org>
(cherry-picked from commit 1c332d4f223066932035578f22877d269443394e)
(cherry-picked from: git://git.linaro.org/people/nico/linux.git)

BUG=chrome-os-partner:19820
TEST=Booted peach

Change-Id: Ib8d37ae97a4cd52b104b363f5e7c02df6b96aacb
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
[abrestic: fixed style errors]
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/59037
ARM: SMP: basic IPI triggered completion support

We need a mechanism to let an inbound CPU signal that it is alive before
even getting into the kernel environment i.e. from early assembly code.
Using an IPI is the simplest way to achieve that.

This adds some basic infrastructure to register a struct completion
pointer to be "completed" when the dedicated IPI for this task is
received.

Signed-off-by: Nicolas Pitre <nico@linaro.org>
(cherry picked from commit 917c352f7ba7753449aa670b49748068f6629cd1)
(cherry-picked from: git://git.linaro.org/people/nico/linux.git)

BUG=chrome-os-partner:19820
TEST=Booted peach

Change-Id: I429709314d9ae8201e484c51034b9f2fec136370
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/59043
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Andrew Bresticker <abrestic@chromium.org>
ARM: mcpm: add a simple poke mechanism to the early entry code

This allows to poke a predetermined value into a specific address
upon entering the early boot code in bL_head.S.

Signed-off-by: Nicolas Pitre <nico@linaro.org>
(cherry picked from commit cfc3179ae13ba52b15e9c8fa9ed805141d09e7d9)
(cherry-picked from: git://git.linaro.org/people/nico/linux.git)

BUG=chrome-os-partner:19820
TEST=Booted peach

Change-Id: I44666c56dc04ad855d438068b81b433977006830
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/59044
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Andrew Bresticker <abrestic@chromium.org>
ARM: bL_switcher: wait until inbound is alive before performing a switch

In some cases, a significant delay may be observed between the moment
a request for a CPU to come up is made and the moment it is ready to
start executing kernel code.  This is especially true when a whole
cluster has to be powered up which may take in the order of miliseconds.
It is therefore a good idea to let the outbound CPU continue to execute
code in the mean time, and be notified when the inbound is ready before
performing the actual switch.

This is achieved by registering a completion block with the appropriate
IPI callback, and programming the sending of an IPI by the early assembly
code prior to entering the main kernel code.  Once the IPI is delivered
to the outbound CPU, the completion block is "completed" and the switcher
thread is resumed.

Signed-off-by: Nicolas Pitre <nico@linaro.org>
(cherry picked from commit 976e214051cea025f8f55624b254a4e8fe44cd53)
(cherry-picked from: git://git.linaro.org/people/nico/linux.git)

BUG=chrome-os-partner:19820
TEST=Booted peach

Change-Id: I5036496225633fe3de67353d7f43e7015550984b
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/59045
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Andrew Bresticker <abrestic@chromium.org>
ARM: bL_switcher: Add synchronous enable/disable interface

Some subsystems will need to know for sure whether the switcher is
enabled or disabled during certain critical regions.

This patch provides a simple mutex-based mechanism to discover
whether the switcher is enabled and temporarily lock out further
enable/disable:

  * bL_switcher_get_enabled() returns true iff the switcher is
    enabled and temporarily inhibits enable/disable.

  * bL_switcher_put_enabled() permits enable/disable of the switcher
    again after a previous call to bL_switcher_get_enabled().

Signed-off-by: Dave Martin <dave.martin@linaro.org>
Signed-off-by: Nicolas Pitre <nico@linaro.org>
(cherry picked from commit 80899af2e864a8a546f6d8f46bccdc1014e9fbd0)
(cherry-picked from: git://git.linaro.org/people/nico/linux.git)

BUG=chrome-os-partner:19820
TEST=Booted peach

Change-Id: I4aee6017f7c4ebc39e61e2e52ecaae10b27444bb
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/59046
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Andrew Bresticker <abrestic@chromium.org>
ARM: bL_switcher: Add runtime control notifier

Some subsystems will need to respond synchronously to runtime
enabling and disabling of the switcher.

This patch adds a dedicated notifier interface to support such
subsystems.  Pre- and post- enable/disable notifications are sent
to registered callbacks, allowing safe transition of non-b.L-
transparent subsystems across these control transitions.

Notifier callbacks may veto switcher (de)activation on pre notifications
only.  Post notifications won't revert the action.

If enabling or disabling of the switcher fails after the pre-change
notification has been sent, subsystems which have registered
notifiers can be left in an inappropriate state.

This patch sends a suitable post-change notification on failure,
indicating that the old state has been reestablished.

For example, a failed initialisation will result in the following
sequence:

    BL_NOTIFY_PRE_ENABLE
    /* switcher initialisation fails */
    BL_NOTIFY_POST_DISABLE

It is the responsibility of notified subsystems to respond in an
appropriate way.

Signed-off-by: Dave Martin <dave.martin@linaro.org>
Signed-off-by: Nicolas Pitre <nico@linaro.org>
(cherry picked from commit 4c9163c32280a10f214f39dc945c5400ef91cd49)
(cherry-picked from: git://git.linaro.org/people/nico/linux.git)

BUG=chrome-os-partner:19820
TEST=Booted peach

Change-Id: If1cd02e4de1fb5f266a3a9f3d01adbd0f5dc5c9d
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/59047
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Andrew Bresticker <abrestic@chromium.org>
ARM: bL_switcher: Add switch completion callback for bL_switch_request()

There is no explicit way to know when a switch started via
bL_switch_request() is complete.  This can lead to unpredictable
behaviour when the switcher is controlled by a subsystem which
makes dynamic decisions (such as cpufreq).

The CPU PM notifier is not really suitable for signalling
completion, because the CPU could get suspended and resumed for
other, independent reasons while a switch request is in flight.
Adding a whole new notifier for this seems excessive, and may tempt
people to put heavyweight code on this path.

This patch implements a new bL_switch_request_cb() function that
allows for a per-request lightweight callback, private between the
switcher and the caller of bL_switch_request_cb().

Overlapping switches on a single CPU are considered incorrect if
they are requested via bL_switch_request_cb() with a callback (they
will lead to an unpredictable final state without explicit external
synchronisation to force the requests into a particular order).
Queuing requests robustly would be overkill because only one
subsystem should be attempting to control the switcher at any time.

Overlapping requests of this kind will be failed with -EBUSY to
indicate that the second request won't take effect and the
completer will never be called for it.

bL_switch_request() is retained as a wrapper round the new function,
with the old, fire-and-forget semantics.  In this case the last request
will always win. The request may still be denied if a previous request
with a completer is still pending.

Signed-off-by: Dave Martin <dave.martin@linaro.org>
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
(cherry picked from commit 0e95b2814e880cb031550d7c812c622df37f9154)
(cherry-picked from: git://git.linaro.org/people/nico/linux.git)

BUG=chrome-os-partner:19820
TEST=Booted peach

Change-Id: I8712c926dab0080468455d25303290eafc935d65
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
[abrestic: fixed style errors]
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/59787