Changed the default memory size for qemu
Separated interrupts and tss initialization
Removed TSS code from interrupts

Placed the TSS specific code into another file
Fixed the data segment descriptor in the GDT

Also set all segment registers (besides CS) to it.
Initial revision of the interrupt handlers

Now uses isr stubs to save/restore the registers. This will still change
because it doesn't support switching processes and the ordering hasn't
been fully thought out yet.
Some helper functions (CPUID, READMSR)

This are needed to setup the processor's APIC for the external interrupts
Initial version of the APIC initialization code.