Xilinx block RAM without inference

*  Implemented a module to create a suitable collection of block RAM
   cells given the parameters in instantiation.  I did this because I
   remember having problem a while ago when trying to infer large RAMs
   in that the Xilinx tools would not connect all of the address signals
   to the inferred RAM.

   Despite this, it is not the problem here.  There is still the
   discrepancy between internal RAM & SDRAM, and the cache I've been
   testing does not use more than one block RAM cell per cache piece.

*  The Xilinx block RAM module does not yet correctly handle byte
   selection for RAMs that are not a multiple of 8-bits wide.