Refactoring
Removed IADD and ISUB

Since doesn't make sense having a signed mode for these instructions.
Change on instruction word construction

Instructions with only one register were constructed like

--------------------------------
| opcode |       register      |
--------------------------------
  5 bits         8 bits

But since has 16 generic registers, their addresses are referenced by
just 4 bits, so makes more sense for a instruction word be constructed
in the following format

--------------------------------
| opcode | register |          |
--------------------------------
  5 bits    4 bits
Increment PC after execute stage (instead of decode)
Complete tests for MOV instruction
ADD instruction
Test for setting most and less significant registers
Handling add transport for smaller registers
Change on ISA

ADD don't handle anymore the excess (transport)
Corrections on OPCODES values
Added way to start cycle from a CPU object

The purpose is to eliminate MachineCycle, merging it with CPU class.
Merged class MachineCycle into class CPU
CPU execution units separated
SUB instruction
OR instruction
AND instruction
XOR instruction
Invalid opcodes now behave as NOP
DIV instruction
MOD instruction