cores: updates and additions

The following changes since commit 03277939d200cd49aa1eb6dd598dd2bcb1fa7123:

  cores: add simple 8-bit gpio core (2013-09-14 23:29:08 +0300)

are available in the git repository at:

  https://github.com/skristiansson/orpsoc-cores.git for-openrisc

for you to fetch changes up to 20a48b2f58edc8672a8db66601daa79bb5af579a:

  cores: add wishbone to avalon bridge core (2013-09-18 05:52:21 +0300)

----------------------------------------------------------------
Stefan Kristiansson (3):
      cores/mor1kx: use 'version' instead of deprecated 'branch' option
      cores: add diila - Device Independent Integrated Logic Analyzer core
      cores: add wishbone to avalon bridge core

 cores/diila/diila.core                               | 13 ++++++++++
 cores/mor1kx/mor1kx.core                             |  2 +-
 cores/wb_avalon_bridge/verilog/avalon_to_wb_bridge.v | 86 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 cores/wb_avalon_bridge/verilog/wb_to_avalon_bridge.v | 83 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 cores/wb_avalon_bridge/wb_avalon_bridge.core         |  8 +++++++
 5 files changed, 191 insertions(+), 1 deletion(-)
 create mode 100644 cores/diila/diila.core
 create mode 100644 cores/wb_avalon_bridge/verilog/avalon_to_wb_bridge.v
 create mode 100644 cores/wb_avalon_bridge/verilog/wb_to_avalon_bridge.v
 create mode 100644 cores/wb_avalon_bridge/wb_avalon_bridge.core