[mips][msa] Implemented copy_[us].d intrinsic.

This intrinsic is lowered into equivalent copy_s.w instructions during
legalization.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191518 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][msa] Implemented fill.d intrinsic.

This intrinsic is lowered into an equivalent BUILD_VECTOR which is further
lowered into a sequence of insert.w's on MIPS32.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191519 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: Teach assembler to enforce constraints for ARM LDRD destination register operands.

As specified in A8.8.72/A8.8.73/A8.8.74 in the ARM ARM, all variants of the ARM LDRD instruction have the following two constraints:

LDRD<c> <Rt>, <Rt2>, ...

(a) Rt must be even-numbered and not r14
(b) Rt2 must be R(t+1)

If those two constraints are not met the result of executing the instruction will be unpredictable.

Constraint (b) was already enforced, this commit adds support for constraint (a).

Fixes rdar://14479793.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191520 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][msa] Implemented insert.d intrinsic.

This intrinsic is lowered into an equivalent INSERT_VECTOR_ELT which is
further lowered into a sequence of insert.w's on MIPS32.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191521 91177308-0d34-0410-b5e6-96231b3b80d8
[SystemZ] Improve handling of PC-relative addresses

The backend previously folded offsets into PC-relative addresses
whereever possible.  That's the right thing to do when the address
can be used directly in a PC-relative memory reference (using things
like LRL).  But if we have a register-based memory reference and need
to load the PC-relative address separately, it's better to use an anchor
point that could be shared with other accesses to the same area of the
variable.

Fixes a FIXME.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191524 91177308-0d34-0410-b5e6-96231b3b80d8
[SystemZ] Rein back the use of block operations

The backend tries to use block operations like MVC, NC, OC and XC for
simple scalar operations.  For correctness reasons, it rejects any case
in which the regions might partially overlap.  However, for performance
reasons, it should also reject cases where the regions might be equal,
since the instruction might then not use the fast path.

This fixes a performance regression seen in bzip2.  We may want to limit
the optimisation even more in future, or even remove it entirely, but I'll
try with this for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191525 91177308-0d34-0410-b5e6-96231b3b80d8
Transforms: Use getFirstNonPHI to set the insertion point for PHIs

We were previously using getFirstInsertionPt to insert PHI
instructions when vectorizing, but getFirstInsertionPt also skips past
landingpads, causing this to generate invalid IR.

We can avoid this issue by using getFirstNonPHI instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191526 91177308-0d34-0410-b5e6-96231b3b80d8
TBAA: handle scalar TBAA format and struct-path aware TBAA format.

Remove the command line argument "struct-path-tbaa" since we should not depend
on command line argument to decide which format the IR file is using. Instead,
we check the first operand of the tbaa tag node, if it is a MDNode, we treat
it as struct-path aware TBAA format, otherwise, we treat it as scalar TBAA
format.

When clang starts to use struct-path aware TBAA format no matter whether
struct-path-tbaa is no, and we can auto-upgrade existing bc files, the support
for scalar TBAA format can be dropped.

Existing testing cases are updated to use the struct-path aware TBAA format.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191538 91177308-0d34-0410-b5e6-96231b3b80d8
Adding intrinsics to the llvm backend for TBM instruction set.
Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191539 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Rewrite MipsTargetLowering::getAddr functions as template functions.

No intended functionality change.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191546 91177308-0d34-0410-b5e6-96231b3b80d8
InstCombine: Only foldSelectICmpAndOr for integer types

Currently foldSelectICmpAndOr asserts if the "or" involves a vector
containing several of the same power of two. We can easily avoid this by
only performing the fold on integer types, like foldSelectICmpAnd does.

Fixes <rdar://problem/15012516>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191552 91177308-0d34-0410-b5e6-96231b3b80d8
Update.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191553 91177308-0d34-0410-b5e6-96231b3b80d8
Re-submit r191472 with a fix for big endian.

llvm-objdump: Dump COFF import table if -private-headers option is given.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191557 91177308-0d34-0410-b5e6-96231b3b80d8
Make SourceMgr::PrintMessage() testable and add unit tests


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191558 91177308-0d34-0410-b5e6-96231b3b80d8
Clarifying doc about cross-compiling

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191561 91177308-0d34-0410-b5e6-96231b3b80d8
SourceMgr diagnotics printing: fix a bug where printing a fixit for a source
range that includes a tab character will cause out-of-bounds access to the
fixit string.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191563 91177308-0d34-0410-b5e6-96231b3b80d8
Fix SLPVectorizer using wrong address space for load/store

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191564 91177308-0d34-0410-b5e6-96231b3b80d8
Resurrect lit.local.cfg to un-break hexagon buildbot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191565 91177308-0d34-0410-b5e6-96231b3b80d8
Object/COFF: Rename getXXX{Begin,End} -> xxx_{begin,end}.

It is mentioned in the LLVM coding standard that _begin() and _end() suffixes
should be used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191569 91177308-0d34-0410-b5e6-96231b3b80d8