HACK: ARM: OMAP4: wakeupgen: Ignore 8th interrupt on GP devices

On OMAP4 GP devices 8th (secure) interrupt is constantly pending.
The source of this interrupt is CONTROL_CORE_SEC_STATUS register.
All its bits are OR'ed and wired to 8th GIC interrupt.
This resister contains power domain reset statuses.

Just after boot CONTROL_CORE_SEC_STATUS has at least one bit set,
so as soon as GIC is initialized in kernel it asserts 8th IRQ to A9.
The register can't be cleared on GP device because it is accessible
for write only from secure privileged mode.

CONTROL_CORE_SEC_STATUS_IRQ_MASK_DISABLE can be used to mask sources
from CONTROL_CORE_SEC_STATUS, but after reset all bits are unmasked
and can be masked only from secure privileged mode.

To workaround this issue on OMAP4 GP devices just ignore
8th interrupt in pending interrupts check.

Change-Id: I6ae41c82bb5b201a5bc9eb735f248be3e86d7a18
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Signed-off-by: Taras Kondratiuk <taras@ti.com>