More VHDL coverage: opcodes, delayed/error WCI responses, "finish", support remote sim containers w/o file access.
Makefile: support "hdlbase" target for everything BUT assemblies
hdl/Makefile: ditto
adapt/os/ocpios/interfaces/include/OcpiOsServerSocket.h: allow fd to be used (for select in sim server)
adapt/os/ocpios/interfaces/include/OcpiOsSocket.h: ditto
adapt/os/ocpios/linux/src/OcpiOsServerSocket.cxx: ditto
adapt/os/ocpios/linux/src/OcpiOsSocket.cxx: ditto
components/bias_vhdl.hdl/bias_vhdl.vhd: props_write changed to props_in for consistency
components/specs/stream_protocol.xml: remove extraneous operation
core/container/hdl/src/SimDriver.cxx: implement sending the bit file over a socket to the server
core/container/hdl/src/SimServer.cxx: ditto
core/local/util/assembly/include/OcpiUtilAssembly.h: simplify external connections
core/local/util/assembly/src/OcpiUtilAssembly.cxx: allow "external" element to externalize ports
hdl/assemblies/demoappC/demoappC.xml: remove "language" since it is now illegal
hdl/assemblies/demoappE/demoappE.xml: ditto
hdl/assemblies/testbias/testbias.xml: ditto
hdl/assemblies/testbias2/testbias2.xml: ditto
hdl/assemblies/testbias5/testbias5.xml: ditto
hdl/assemblies/testbias_ver/testbias_ver.xml: ditto
hdl/assemblies/testddc/testddc.xml: ditto
hdl/assemblies/testpsd/testpsd.xml: ditto
hdl/assemblies/testwbr/testwbr.xml: ditto
hdl/assemblies/tb_bias/Makefile: use hdl-assy.mk, not hdl-app.mk
hdl/assemblies/tb_bias_vhdl/tb_bias_vhdl.xml: remove language, simplify connections
hdl/primitives/ocpi/control_decoder.vhd: add error signal to return errors on wci
hdl/primitives/ocpi/decoder.vhd: ditto, and allow config accesses to be delayed by worker
hdl/primitives/ocpi/wci_pkg.vhd: ditto, plus some cleanup, plus adding the "finished" bit on sflag(2)
hdl/primitives/ocpi/master.vhd: add byte width to do data/data-info properly - support bytesize != 8
hdl/primitives/ocpi/slave.vhd: ditto
hdl/primitives/ocpi/wsi_pkg.vhd: ditto
hdl/primitives/ocpi/proptypes.cpp_gen: deal with property offset being ieee unsigned (can now be > 31 bits)
hdl/primitives/ocpi/property_decoder.vhd: ditto: width matching error in property decode
jkvm6.sh: update license file for modelsim
tools/cdk/include/hdl/hdl-platform.mk: force the OnlyTarget to be this platform
tools/cdk/include/hdl/hdl-pre.mk: nicer error message for libraries that aren't built for the target
tools/cdk/include/hdl/hdl-worker.mk: force, internally, the language of assemblies to be verilog
tools/cdk/include/lib.mk: also remove gen subdir on cleaning
tools/cdk/ocpigen/ocpigen/include/wip.h: record whether there are any props needing worker readback
--- volatile or read and !write
--- also endian parsing support
tools/cdk/ocpigen/ocpigen/src/wip_HDL.cxx: add support for readable, non-volatile, not-writable properties
--- also support the worker delaying wci accesses, and possibly indicating errors
--- all full opcode support with enumerations
--- also "finish" status added to sflag(2) - this is a partial solution - more needs to be done
--- also add VHDL WTI support
--- also some cases of burstlength (precise)
--- also endian support
tools/cdk/ocpigen/ocpigen/src/wip_parse.cxx: parsing support for above, remove "language" from hdlassy
tools/cdk/ocpigen/ocpigen/src/wip_OCP.cxx: make sflag 3 bits wide for "finished"
Complete sim server file transfer feature, add "finish" output from HDL, and spartan6 target
adapt/os/ocpios/linux/src/OcpiOsClientSocket.cxx: fix debug print to use ocpiDebug
adapt/os/ocpios/linux/src/OcpiOsServerSocket.cxx: let destructor do the "close" if needed
components/bias.hdl/bias.v: add sflag(2) to the BSV-generated verilog
components/capture.hdl/capture.v: ditto
components/ddc.hdl/ddc.v: ditto
components/delay.hdl/delay.v: ditto
components/framegate.hdl/framegate.v: ditto
components/pattern.hdl/pattern.v: ditto
components/psd.hdl/psd.v: ditto
components/sma.hdl/sma.v: ditto
components/splitter2x2.hdl/splitter2x2.v: ditto
components/wbr.hdl/wbr.v: ditto
core/container/hdl/src/NetDriver.cxx: bug fix in new udp command responses
core/container/hdl/src/SimDriver.cxx: debug new file transfer socket mode from driver to server
core/container/hdl/src/SimServer.cxx: ditto
hdl/assemblies/Makefile: another "application"->"assembly" message fix
tools/cdk/include/hdl/hdl-targets.mk: add spartan6 target and iveia Atlas 1 lpe platform
tools/cdk/include/hdl/xst.mk: ditto