posix-test:fix times test

Applications should use sysconf(_SC_CLK_TCK) to determine the number
of clock ticks per second as it may  vary  from system to system.
arm:timer changes.

* Allow to change the timer frequency using the hz paramter.
* Unmask the interrupt only after registering the handler.
* Pass the hz parameter in the command line.
arm:use correct address mask for sections.
arm:misc fix remove const modifier for value that changes.

Change-Id: I4ac96acdc66ea203a339108225c07c68959556c0
block-dev:add additional sanity check.

Change-Id: Ib5b7cd93a50726b95c2e1b4c7eeedfefc824dd9c
arm:allow to lookup physical addresses of sections.

Change-Id: If4716b81cceee5d8b30d5f103b772b0ac99fc807
arm:vm map free running clock uncached.
arm:define the physical memory range for the omap.

Change-Id: I256dbeb58fec5b95b48d521054810fe478fce67f
arm:document arm vm.h
arm:clarify pagetable code.

Make it clear that non RW mapped memory is mapped RO.
arm:caching introduce _CACHED defines

Introduce ARM_VM_SECTION_CACHED and ARM_VM_PTE_CACHED to ensure we
are using the correct caching flags everywhere.
arm:caching mark memory as cacheable.

kernel mappings that are not marked as  VMMF_UNCACHED are now mapped
as cacheable.
arm:caching define a new caching combination and use that.

This combo was taken from the startware examples.

Change-Id: I9ef8d4f4706124a6aaec72f5da65b5301c5c2301
arm:caching add methods to flush the data and unified cache

Change-Id: Idb066dd01afbdbccd684bcdcf4af88b4b1ef870a
arm:make the MMU fetch pagetable data through the caches.

Change-Id: Ibd7b66558c369d0c0792c02801562580d255fa1f
arm:perform copy operation using same cacheability.

When copying data from cacheable memory also use cacheable
attributes when creating temporary mappings.

Change-Id: I0e8380293fb4edaafba49f6262983ad86a5350c5
arm:caching access the l1 pages over cacheable memory.

When we start using a new pagetable (for a new process)
the last part is to ensure the pagetable itself can be
accessed by VM. This is done in pt_bind by updating
the "pagetable of pagetables" and we want this mapping
to match other mappings to the l1 pagetable.

Change-Id: I7b506fd75553917fdc1abd25b55e4b2f25ccbf8d
arm:caching mark normal memory cacheable during identity mapping.

Change-Id: I7cd8da168744a3f32276803e99e8af0fea772574
arm:vm allow per memory type flags.

Change-Id: Id5a5bd479bdfbbc3fb52a85c29e1d7712a1171a7
arm:caching clean caches before setting up mappings.

Change-Id: I9ff1bb04ea9c0adeb76e5176526448d93bfe29f5