metag: perf: fix core internal / perf channel mux

The value written to the PERF_ICOREx or PERF_CHANx register to select
the performance events for the core internal and perf channel events was
(tmp & 0x0f), but tmp was set to (config & 0xf0) so it would always be
0. Correct it to use config instead of tmp.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@ghostprotocols.net>
metag: perf: fix wrap handling in delta calculation

When calculating the delta, mask with MAX_PERIOD (24 bits) to handle
wrapping, which particularly happens with periodic sampling since the
value is intentionally set so that it will overflow soon.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@ghostprotocols.net>
metag: perf: fixes for interrupting perf counters

The overflow handler needs to read modify write when re-enabling the
counter so as not to change the counter value as it may have been
changed to ready the next interrupt on overflow. Similarly for
interrupting counters metag_pmu_enable_counter needs to leave the
counter value unchanged rather than resetting it to zero.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@ghostprotocols.net>
metag: perf: add missing prev_count updates

The prev_count needs setting when changing the counter value, otherwise
the calculated delta will be wrong, which for frequency sampling
(dynamic period sampling) results in sampling at too high a frequency.

For non-interrupting performance counters it should also be cleared when
enabling the counter since the write to the PERF_COUNT register will
clear the perf counter.

This also includes a minor change to remove the u64 cast from the
metag_pmu->write() call as metag_pmu->write() takes a u32 anyway, and in
any case GCC is smart enough to optimise away the cast.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@ghostprotocols.net>
metag: perf: fix frequency sampling (dynamic period)

Frequency sampling mode dynamically adjusts the sample period so as to
hit a particular frequency of samples. The sample period starts at just
1 and then gets increased if the interrupt rate is too high. This
changed sample period needs handling in metag_pmu_event_set_period to
update period_left (as the ARM equivalent does). The calculated delta
also needs subtracting from period_left in metag_pmu_event_update in
order to hit the conditional blocks in metag_pmu_event_set_period which
update last_period (which is used in the dynamic sampling period
calculation).

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@ghostprotocols.net>
metag: perf: use hard_processor_id() to get thread

Use hard_processor_id() to get the current thread number rather than
get_cpu() and the hardware thread mapping. There was no matching
put_cpu(), and in any case this should be slightly more efficient.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@ghostprotocols.net>
metag: perf: don't reset TXTACTCYC

The thread active cycle counter TXTACTCYC is used in __delay so it
shouldn't really be reset to zero by perf. Fix perf to just read the
value, and instead of clearing it, record the prev_count value in
enable_counter so that the delta calculations know about the previous
value.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@ghostprotocols.net>
metag: perf: prepare for use by oprofile

To allow our perf_events code to work with oprofile the PERF_TYPE_RAW
event type attribute is implemented, which allows the internal encoding
of events to be used externally (this requires some tweaks so that it
handles invalid event types more gracefully), and perf_pmu_name() is
adjusted to return metag_pmu->name instead of metag_pmu->pmu.name (which
is changed to "meta2").

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@ghostprotocols.net>
Cc: Robert Richter <rric@kernel.org>
Cc: oprofile-list@lists.sf.net
metag: OProfile support

Add OProfile support for metag, using the perf backend, and falling back
to generic timer based sampling if perf counter interrupt support is
disabled.

The oprofile code prepends "metag/" to the perf pmu name to give
"metag/meta2" which is more consistent with other oprofile arch names.

The backtrace code makes use of <asm/stacktrace.h> for kernel
backtracing, and a simple frame pointer walk for userland backtracing.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Robert Richter <rric@kernel.org>
Cc: oprofile-list@lists.sf.net
metag: smp: copy cache partition and enable GCOn

When starting an SMP hardware thread, copy the cache partition
configuration so that the threads share the same cache partitions. Also
enable the GCOn bit if running in the local half of the virtual address
space to enable coherency of shared local cache partitions. An atomic
unlock system event is executed by the new cpu before any memory is read
to ensure that any writes made by the boot cpu prior to full coherency
taking effect are visible to the new cpu.

This is to allow SMP to work even when the bootloader hasn't configured
the caches for coherency. A log message is printed to describe the cache
partition changes so that the user is aware of potential unintentional
cache wastage if they've configured the cache partitions in the wrong
way.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
metag: cachepart: take into account small cache bits

The CORE_CONFIG2 register has bits to indicate that the data or code
cache is small, i.e. that the size described in the field should be
divided by 64. Take this into account in get_icache_size() and
get_dcache_size().

Signed-off-by: James Hogan <james.hogan@imgtec.com>
metag: cachepart: fix get_global_dcache_size() typo

Compilation is broken when the kernel is destined to live in the global
part of the virtual address space:

arch/metag/kernel/cachepart.c In function 'get_thread_cache_size':
arch/metag/kernel/cachepart.c +71 : error: implicit declaration of function 'get_global_dache_size'

Fix the typo.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
memblock: Kill ARCH_POPULATES_NODE_MAP once more

The Kconfig symbol ARCH_POPULATES_NODE_MAP was killed in v3.3. After
that it popped up again in microblaze and metag. Nobody noticed,
probably because these Kconfig symbols are entirely unused and these
architectures both select HAVE_MEMBLOCK_NODE_MAP. Anyhow, these two
entries can also be killed.

Signed-off-by: Paul Bolle <pebolle@tiscali.nl>
Acked-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: James Hogan <james.hogan@imgtec.com>
arm64: add read_cpuid_{implementor,part_number,mpidr}

In order to preserve some kind of source compatibility between
arm and arm64, introduce read_cpuid_{implementor,part_number,mpidr}
which are used on KVM to find out which CPU we're running on.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
arm64: early_printk: add support for FastModel console output

Enable early_printk to use the FastModel semihosting to output
the early kernel messages. Works both for host and guest kernels.

To use this feature, pass "early_printk=smh" to the kernel.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
arm64: add support for 8250/16550 earlyprintk

This patch adds support for using earlyprintk with 8250/16550 UART
ports. The 8250/16550 UART can either have 8-bit or 32-bit aligned
registers which is HW vendor dependent.

Kernel args for 8-bit aligned regs: earlyprintk=uart8250-8bit,<phys_address>

Kernel args for 32-bit aligned regs: earlyprintk=uart8250-32bit,<phys_address>

Signed-off-by: Anup Patel <anup.patel@linaro.org>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
arm64: Initialise the clocks described via DT

This patch adds an arch_initcall() for the of_clk_init() clock
initialisation.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
arm64: kernel: make the pen of the secondary a 64-bit unsigned value

Change the prototype of write_pen_release() accordingly and clarify
that's holding the hardware id of the secondary that's going to boot.
This is in preparation of getting HWIDs parsed from the DT.

Signed-off-by: Javi Merino <javi.merino@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
arm64: kernel: initialise cpu_logical_map from the DT

When booting the kernel, the cpu logical id map must be initialised
using device tree data passed by FW or through an embedded blob.

This patch parses the reg property in device tree "cpu" nodes,
retrieves the corresponding CPUs hardware identifiers (MPIDR) and
initialises the cpu logical map accordingly.

The device tree HW identifiers are considered valid if all CPU nodes
contain a "reg" property, there are no duplicate "reg" entries and the
DT defines a CPU node whose "reg" property defines affinity levels
that matches those of the boot CPU.

The primary CPU is assigned cpu logical number 0 to keep the current
convention valid.

Based on a0ae02405076ac32bd17ece976e914b5b6075bb0 (ARM: kernel: add
device tree init map function).

Signed-off-by: Javi Merino <javi.merino@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
arm64: head: match all affinity levels in the pen of the secondaries

The reg property of the cpu nodes in the DT now contains all the
affinity levels in (MPIDR[39:32] and MPIDR[23:0]) and that's what
boot_secondary() writes in the pen, so increase the mask in
secondary_holding_pen accordingly.

Signed-off-by: Javi Merino <javi.merino@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>