OMAP3: SDRC : Errata 1.176 Fix - Accesses to DDR stall in SDRC after a Warm-reset

Original patch: http://www.mail-archive.com/linux-omap@vger.kernel.org/msg21030.html

Modified as in latona 2.6.35.
OMAP3: PM: make secure ram save size configurable

OMAP3 users of HS/EMU devices at times choose to use their
own PPA which could be configured to use different sized storage
area based on their security needs. Convert the hardcoded size
define to a more configurable form to map to these users. we introduce
the structure omap3_secure_copy_data to describe PPA specific behavior
we will further populate in follow on patches. secure_copy_data_set
is introduced to allow for board files to populate custom parameters
as desired.

Signed-off-by: Nishanth Menon <nm@ti.com>
board-latona: increase secure ram size

As it was in latona 2.6.35.
OMAP3: PM: latona: disable INTC AUTOIDLE before saving secure RAM
board-latona: do not program the SDRC CS1 registers
Revert "latona: Skip Reprogramming of SDRC clock since dpll3 clock is not found."

This is not required, no errors are thrown.

This reverts commit 7c16104a0faff4ae9518cc5c1418e8b7afa97eed.
OMAP3: PM: don't attach McBSP2 interrupts

Taken from latona 2.6.35.
board-latona: set twl4030 GPIO debounce
latona defconfig: disable SDRC AC timing register changes

It's causing random system crashes.
Merge branch 'cm-10.2-rebased' of git://github.com/sconosciuto/android_kernel_samsung_latona into cm-10.2