Merge branch 'master' of https://github.com/ska-sa/mlib_devel
Merge branch 'master' of https://github.com/ska-sa/mlib_devel
reorder timing improvement

working_values dual port ram now uses casper_library version to improve timing.
Various small timing related improvements.
bus_delay mod

changed delay names to 'del<n>' rather than 'delay<n>' as Simulink
does not allow child blocks to have the same name as the parent and
bus_delay blocks often used with 'delay<n>' as name in scripts.
delay_srl mod

second delay element in chain implemented with 'reg_retiming' set to
'on' so that it can be combined with subsequent delays to reduce logic use.
bus_register license

GPL license terms added to top of script
reorder block mod

fanout_latency and n_bits added to mask parameters.

n_bits allows the use of bus_single_port_rams for data buffers (instead of standard single port rams).
This allows the fanout of address and control signals to be controlled. If n_bits is left at 0 (the default),
the previous behaviour is preserved to preserve backwards compatibility.

fanout_latency controls the amount of latency to be used in the controlling
of fanout into these buffers. The default is 0 to preserver script backwards compatibility.
feedback_osc timing upgrade

feedback_osc used a registered data path that was difficult to make timing with.
Architecture changed to have a small buffer of values that gets updated from
a synchronous data path. This removes one mux and eases timing significantly.

Various other small timing improvements.
bus_mux n_inputs mask parameter added

The default behaviour of bus_mux is to divide a single bus input into
portions and use a multiplexer to choose between them. If n_inputs > 1
this changes to dividing multiple buses into portions and multiplexing
between them.

This allows the control of fanout on the sel input where
very large multiplexers are required (or where the sel input to every mux
is not the same).
cosin timing improvements

rom changed to use 'Speed' as optimization strategy so that large
lookups are still fast (should only change BRAM usage for very large
roms).

Adder in address generator changed to use behavioral_HDL as implementation
option so that trivial additions for certain cases can be optimised away.
coeff_gen minor mods

latencies passed by value rather than refence to force updating of
lower level blocks immediately rather than on update.
bi_real_unscr_4x_init reorder mod

reorder blocks now implemented to use n_bits and fanout_latency parameters
introduced in previous commit. These allow large buffers within the reorder
blocks to be implemented such that fanout is controlled of input signals.
mirror_spectrum mux mod

muxes replaced with bus_muxes so that the fanout of the sel input
of each mux can be controlled. bus_replicate blocks are used to
replicate the sel input appropriately.
fft_unscrambler upgrade

script now uses n_bits and fanout_latency on reorder block to control
fanout within the reorder block.
twiddle_general_init small mod

fanout latency on bus_mult block now determined by number of streams
rather than fixed value.
fft_stage_n timing upgrade

delay_brams replaced with bus_single_port_rams and counters. The counters
are now free running to reduce logic required to figure out when at end of
count. Also allows the output registers on the brams to not have to be registered,
reducing fanout.

Fanout of en signal controlled.

TODO: redo to use bus_muxes as large muxes cause timing issues in the logic
around them (brams at input and output).
butterfly_direct mux mod

muxes replaced with bus_muxes and shift input replicated to reduce fanout.
Merge branch 'master' of https://github.com/casper-astro/mlib_devel
Merge branch 'master' of github.com:ska-sa/mlib_devel