ARM: tegra: lp0 WAKE2 status clear

Tegra pmc WAKE2 status registers also need to be cleared
before re-entering lp0 mode.

Change-Id: I1bd5c48baf86ba23d0352594e97c360d363ce991
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: http://git-master/r/121185
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: David Savage <bedalus@gmail.com>
mm: Fix incorrect cache attribute restoration.

armv7 uses cache policy as WRITEALLOC. CPA is
restoring the cache attributes to WRITEBACK during
set_pages_array_wb().
Fixed issues in pmd to pte prot translation and vice versa.

Change-Id: I8406b784f62d559f657ef7bc08e77c83ac6e5690
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/122472
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Signed-off-by: David Savage <bedalus@gmail.com>
Improve async I/O latency for SSD-like storage potentially 34% improvement to I/O latency

Signed-off-by: David Savage <bedalus@gmail.com>
Mess with several things to make partial reverts a headache
GPU OC thanks nik3r
https://github.com/niker/elitekernel_oxp/blob/jellybean/arch/arm/mach-tegra/tegra3_dvfs.c
ARM auto hotplug by Will Tilsdale

Signed-off-by: David Savage <bedalus@gmail.com>