OMAPDSS: DISPC: more precise scale limits checking

Use division with rounding-up when checking if maximum downscale ratio
was reached. This allows to avoid SYNC_LOST errors in case when small
amount of extra pixels or lines (usually 1-3) not taken into account

Change-Id: Id8f88c64671146a64738cfd820378bb7a28c1455
Signed-off-by: Sergiy Kibrik <sergiy.kibrik@globallogic.com>
(cherry picked from commit 1e51b4145d63d337cacea6f3829bfa2904e28001)
OMAPDSS: DISPC: fix pclk divisor limits

According to TRM, minimal pixel clock divisor value can be 1.
Fix corresponding checks, as high resolution panels use undivided
pixel clock frequency.

Also certain scaler unit constraint must be met: in case DISPC_CLK
and pixel clock frequencies are equal, set IPC to work on rising edge.

Change-Id: Iabeac2ad81f6909213cb81f4e16b1d0762369b53
Signed-off-by: Sergiy Kibrik <sergiy.kibrik@globallogic.com>
Signed-off-by: Lajos Molnar <lajos@ti.com>
Signed-off-by: Dima Svetlov <svetlov@ti.com>
(cherry picked from commit 4a7fe1304453d5cde228caa9f22ce93b9f52528e)