Forgot to reset between test cases.

This showed that the previously commited design was not entirely correct,
as the voter was not enabled quickly enough for a discrepancy in the
first bit to be registered in the state. One way to solve this would be to
delay the operation of the circuit with one cycle, so that we enable the circuit
in time. Another would perhaps be to make the input_ready signal an SR latch
instead of an SR flip flop as it currently is, but latches are perhaps scary?