Multiplexed low-rate FIR (only multipliers, need to work on adders)
Merge branches 'master' and 'mydevel'
Adding l8_ver102.mdl to the repo and correcting a path mismatch in l1
Added black-box related files for mode l8
Remove the redundant *.log file
Update scripts and added bofs
Added mode_sel for mode l8
Adding l1 fpga design versions 101,102,103,104
Updated scripts for l8_lbw8; removed some out-dated functions
Added relatively cleaned up version of l8; Basically the same as ver104 just re-aligned some blocks, etc.
Revert "Added relatively cleaned up version of l8; Basically the same as ver104 just re-aligned some blocks, etc."

That was a mistake

This reverts commit 4512011263a7f34249ac5659ce613280882405b9.
Added SSG to version l8, and compiled (@1.2GHz). Updated script for l8_lbw8
Added relatively cleaned-up version of l1 without real changes... and recompiled. (Timing check disabled)
Based on version 104. BTW last commit of l8 has some cleaning-up as well.
Added l8_ver118 which fixes the order of the SSG status bits.

The new order of the status bits (which coincides with the HPC
code is 3. Blank 2. SR1 1. SR0 0. CAL

The corresponding BOF file has also been added.
Added l1_ver106.mdl to the repository.

This only changes the order of the status bits to coincide
with the HPC code.  The order out is now 3. BLANK 2. SR1
1. SR0 0. CAL
Added h1k_ver101.mdl and h16k_v34101.mdl.

The status bits have been changed in these designs to coincide
with the HPC code.  3. BLANK 2. SR1 1. SR0 0. CAL
Added the h16k bof with the re-ordered status bits.
Renamed h1k scripts to match other modes in newscripts directory.
Added l8_ver119 and its boffile
Adding version 121 of the l8 design.

This version adds delay in front of each of the 8
subbands and allows the design to be clocked at
188MHz.