when led 5 and led 6 is changed, the design compiles and runs smoothly (without correct alignement), but there is a problem with the base address when using the nios 2 core
changed clk speeds to 100 and 10 MHz, now two channels are distorted, but syncronization is proper again
design compiles. sync routine proper. 1 channel slightly disstorted. cmv_master.vhd state from burst to readreq checked -> not necessary
changed dvi process in dvi_master.cmv... now it looks very promising. the sync seq is correct, also horizontal alignement. there are vertical stripes again... no disstortion at all. if only one frame is requested, it seems that the frame is completely correctly aligned.