msm: mdss: Fix ARGC copy size from user

User cfg for ARGC gives varying number of rgb stages. Fixed ARGC config
to only copy data based on number of RGB stages.

Change-Id: I425527b12364b03bbcd8c9d984a2675cd8444d62
Signed-off-by: Benet Clark <benetc@codeaurora.org>
msm: smd_pkt: add device tree support

SMD PKT is configured using local tables that do not allow customization
on a per-target basis.

Add device tree support to configure SMD PKT devices.

Change-Id: Ife4e6085ab4548a373fa79fc11eabc319a2aa146
Signed-off-by: Arun Kumar Neelakantam <aneela@codeaurora.org>
ARM:dts:msm: Remove CPU notifications to RPM for MSM8226v2

RPM uses SPM signals from L2 and each of the APPS core to
determine if it is okay to transition from active set to
sleep set. On 8x10 and 8x26 due to a Cortex-A7 ARM errata
where primary core(C0) when waking up from power collapse
has to wake up all the secondary cores to invalidate
all it's L1 duplicate tag RAMs and power collapse them
again. Due to this there is an unnecessary increase in
SPM-RPM handshake interrupts for secondary cores.

This patch removes the APPS cores notification to RPM in
RPM assisted PC and only L2 handshakes with RPM. This helps
to reduce the interrupt traffic generated by APPS cores to
RPM.

CRs-Fixed: 524102
Change-Id: Ieafacdab811d2571965b91e5772663e84a89b896
Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org>
ARM:dts:msm: Remove CPU notifications to RPM for MSM8226v1

RPM uses SPM signals from L2 and each of the APPS core to
determine if it is okay to transition from active set to
sleep set. On 8x10 and 8x26 due to a Cortex-A7 ARM errata
where primary core(C0) when waking up from power collapse
has to wake up all the secondary cores to invalidate
all it's L1 duplicate tag RAMs and power collapse them
again. Due to this there is an unnecessary increase in
SPM-RPM handshake interrupts for secondary cores.

This patch removes the APPS cores notification to RPM in
RPM assisted PC and only L2 handshakes with RPM. This helps
to reduce the interrupt traffic generated by APPS cores to
RPM.

CRs-Fixed: 524102
Change-Id: I1bd0f66d648cae88ff9f3ca82fcb19911b9c6c52
Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org>
ARM:dts:msm: Remove CPU notifications to RPM for MSM8610

RPM uses SPM signals from L2 and each of the APPS core to
determine if it is okay to transition from active set to
sleep set. On 8x10 and 8x26 due to a Cortex-A7 ARM errata
where primary core(C0) when waking up from power collapse
has to wake up all the secondary cores to invalidate
all it's L1 duplicate tag RAMs and power collapse them
again. Due to this there is an unnecessary increase in
SPM-RPM handshake interrupts for secondary cores.

This patch removes the APPS cores notification to RPM in
RPM assisted PC and only L2 handshakes with RPM. This helps
to reduce the interrupt traffic generated by APPS cores to
RPM.

CRs-Fixed: 524102
Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org>
Change-Id: I45cf7d87081ee6aa78829ac3470f6c02879a6463
platform: qpnp-power-on: Add sysfs entry for debounce

Add sysfs entry to dynamically configure debounce time
for PON module from userspace.

CRs-fixed: 524716
Change-Id: I647e96f874a5d1141ada564d838fd2c63f1b8a13
Signed-off-by: Mohan Pallaka <mpallaka@codeaurora.org>
slim_ngd: Handle runtime-pm resume error gracefully

Runtime-pm resume for satellite driver may fail if ADSP is going
through subsystem-restart. Handle that error, and set runtime-pm's
status to suspended if resume fails. Resume typically fails due to
failure to wake slimbus from pause_clock. Make sure another wakeup
can be tried later when ADSP comes back up

Change-Id: Ie9b798f5506de89a37491dbc3798acaa24b98808
Signed-off-by: Sagar Dharia <sdharia@codeaurora.org>
msm: camera: Fix potential memory overflow errors

Fix potential memory overflow errors in msm_isp_util.c which happen
under certain rare conditions.

CRs-fixed: 514717
Change-Id: I8c70e089df9bf1e7a364c5c8264b782c9c23bf0b
Signed-off-by: Seemanta Dutta <seemanta@codeaurora.org>
arm/dts: 8610: Enable continuous splash screen for
8x10 QRD SKUAB

Enable continuous splash screen for 8x10 QRD SKUAB

Change-Id: I225988c7493efd2caec434ca3df249c9d89c1579
Signed-off-by: Shuo Yan <shuoy@codeaurora.org>
arm: dts: msm: Configure FCC learning parameters for 8226 MTP and QRD

Set the Full Charge Capacity (FCC) learning parameters
and enable FCC learning.

CRs-Fixed: 417288
Change-Id: I63a25df72fc9e758057e64ecf5f3ca8ba41364b9
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
scsi: ufs: add debugfs for ufs

Adding debugfs capability for ufshcd. This patch also implements
command tag statistics enabling, disabling, printing and resetting.

Change-Id: Idea0323391029c446a0a75aa5bea7070e3ab8125
Signed-off-by: Lee Susman <lsusman@codeaurora.org>
msm: mdss: fix the tearing issue on 8x10

Configure the tearing check related registers properly
to resolve the tearing issue on 8x10 DSI command mode.

Change-Id: If50239375758e68a115a044d04eddf6285c62bda
Signed-off-by: Xiaoming Zhou <zhoux@codeaurora.org>
ARM: dts: Disable VFE and Oxili power-collapse modes for 8610

Restore of power to VFE memories may cause droop on the MX power
rail, and restore of Oxili power may cause droop on the CX rail.
Disable these power-collapse features for now until they are shown
to be safe. VFE GDSC collapse is also disabled since the VFE logic
must remain powered if the memory periphery is powered.

Change-Id: I5452e5c70172cc71fb3b8cc09276ac7b3ad99cc7
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
msm: kgsl: Implement the A3XX power-on shader workaround

On some targets (A330v2) the hardware is in a wonky state following
a power collapse. Send a special command buffer before the first
submission to put everything back in place.

Change-Id: Ic0dedbadb8e676677b9db95defd53f7bd3fba338
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
power: qpnp-charger: workaround for coupling issue

On 8x26, the IADC current readings are off when the battery is charging
and is below 3.8V.

This bug is attributed to charger buck switching with high frequency
especially when the battery voltage is significantly lower than the input
charger voltage. As the battery charges up its voltage increases,
charger starts going towards high duty cycle mode thereby reducing the
switches. This reduction in switches improves the IADC accuracy.

Implement workarounds when the battery voltage is lower than 3.8V and is
in a fast charging state. Reduce the number of power stages helps with
improving the IADC accuracy.

Note that this workaround only needs to be applied when a USB Wall
charger or USB CDP is present. With USB SDP the input current is too low
to cause IADC inaccuracies.

Change-Id: Ie7e067973a96d478005ddfdddae7c8c0dc394071
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
ARM: dts: msm: Change OV5648 display orientation

Change DTS file to alter front camera display orientation.

Change-Id: I764b8defface38ecc9fbb4dd5c8b2e3a912118c8
Signed-off-by: Su Liu <suliu@codeaurora.org>
msm: perf: Fix debug node permissions

Fix testAllFilesInSysAreNotWritable failure by changing permissions
for [/sys/kernel/debug/perf_debug_tp/enabled] from 0777 to 0660

CRs-Fixed: 522471
Change-Id: Iea7fc2072ea00f011fd7a91fd16c936e42272b14
Signed-off-by: Sheetal Sahasrabudhe <sheetals@codeaurora.org>
ARM: dts: msm: modify memory reservation requirements for tmc-etr on 8974

The CoreSight TMC-ETR driver is modified to meet its coherent memory
allocation requirement using dma_alloc_coherent api instead of custom
allocate_contiguous_ebi function. Add support to the device tree to
specify this memory requirement.

Also retain the dt entry to allocate contiguous memory via
allocate_contiguous_ebi api until the corresponding driver changes go
in to prevent breaking TMC-ETR functionality.

Change-Id: I67b4813ab45d520311765500513ea265fb33188e
Signed-off-by: Aparna Das <adas@codeaurora.org>
ARM: dts: msm: modify memory reservation requirements for tmc-etr on 9625

The CoreSight TMC-ETR driver now meets its coherent memory allocation
requirement using dma_alloc_coherent api instead of custom
allocate_contiguous_ebi function. Add support to the device tree to
specify this memory requirement.

Also retain the dt entry to allocate contiguous memory via
allocate_contiguous_ebi api until the corresponding driver changes go
in to prevent breaking TMC-ETR functionality.

Change-Id: I7e6288ad8a7c7583636ef221888e1774ba40d3ba
Signed-off-by: Aparna Das <adas@codeaurora.org>
ARM: dts: msm: modify memory reservation requirements for tmc-etr on 8226

The CoreSight TMC-ETR driver now meets its coherent memory allocation
requirement using dma_alloc_coherent api instead of custom
allocate_contiguous_ebi function. Add support to the device tree to
specify this memory requirement.

Also retain the dt entry to allocate contiguous memory via
allocate_contiguous_ebi api until the corresponding driver changes go
in to prevent breaking TMC-ETR functionality.

Change-Id: I0aaab3aa2d79aac0c8cc523fe33e00ca55e0fac7
Signed-off-by: Aparna Das <adas@codeaurora.org>