Merge pull request #2 from skristiansson/for-openrisc

cores: update mor1kx.core files
wb_bfm: Added wb_bfm_transactor
Remove deprecated core wb_utils

Users of wb_utils should migrate to wb_intercon instead.
This will break the (probably already broken) generic system
wb_sdram_ctrl: Added simulation support
wb_intercon: Rename sdt to rdt in wb_arbiter
wb_intercon: Rewrite wb_mux to avoid placing select logic outside of module

wb_mux previously used a slave_sel_i input and required that the slave
select logic was placed outside the module.
This is changed so that the parameters MATCH_ADDR and MATCH_MASK are used
to select slaves instead. Updates to the test bench are in this commit too
wb_intercon: Replace internal wb_master with wb_bfm_transactor
or1200-generic: Adapt to changes in wb_intercon
or1200-generic: Add UART simulation model
Add core mt48lc16m16a2
wb_intercon: replace rdt/sdt with wb spec compliant name (dat)

Using non-standard names on signals in a standardised bus is
confusing for users, so that should be avoided.
However, the naming convention (sdt/rdt instead of dat for
slave data), served a purpose. It avoids the issue of two
signals having the same name when interconnectnig cores.

This patch takes a different approach and insert direction
markers into the signal names in modules where interconnect
occurs. The markers are: 'm2s' for 'master to slave' signals
and 's2m' for 'slave to master' signals.