wb_intercon: add generation of instantiation template

This make wb_intercon_gen generate a template instantiation of
the module it has created, with associated wires.
The template is generated in the form of a header file, which
is intended to be `included in the target design.
or1200-generic: use wb_intercon_gen template header file
Merge branch 'de0_nano' of https://github.com/skristiansson/orpsoc-cores
add .gitignore
cores: add altera_virtual_jtag core

Used as a wrapper to altera virtual jtag by advanced debug sys,
but isn't limited to that.
de0_nano: use common altera_virtual_jtag core
cores: mt48lc16m16a2: core is now fetched from micron's url

Import Micron's original file and add patches for:

- changing EOL from Dos to Linux,
- add an parameter to clear the SDRAM before it is used,
- add tasks to get/set bytes/sorts in the whole memory,
- turn off the debug messages.

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
Merge branch 'for-openrisc' of https://github.com/skristiansson/orpsoc-cores
cores: mt48lc16m16a2: change MEM_SIZES to lower case in patch 0004

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
cores: adv_debug_sys: For X to zero during sim in crc module

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
wb_intercon: assert wbm_err_o on non-match accesses

Instead of falling back to the first slave when no match occur,
signal a wishbone error. If fallback behaviour is desired,
it's still acheivable by extending the range of the slave
to which the fallback is desired.
avalon_to_wb_bridge: abort read on wbm_err_i
cores: add vga_lcd core

This adds the vga_cld core from opencores, with two accompanying
patches.
One for a typo of a signal and one for fifo auto resync.
Merge pull request #12 from fjullien/for-upstream-new

cores: adv_debug_sys: Force X to zero during sim in crc module
Merge pull request #13 from skristiansson/for-openrisc

cores: updates fixes and additions
wb_avalon_bridge: wb burst to avalon pipeline access translation

Since there is no way of knowing what kind of (avalon) bursts
are suppported by the slaves we connect to, the wishbone bursts
are translated into avalon pipelined reads rather than avalon
bursts.
Wishbone allows for bursts to be ended at arbitrary cycles
(with the 'end burst' commmand), such cases are handled by
waiting out the remaining pending reads and filtering out the
readdatavalid signal from the wb_ack signal.
cores: uart16550: fix wb slave behavior

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
systems: add Altera de1 board support

This is a minimal port. VGA, SD-CARD and PS2 will come later.

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
Merge branch 'for-upstream-new' of https://github.com/fjullien/orpsoc-cores
Merge branch 'for-openrisc' of https://github.com/skristiansson/orpsoc-cores