generic_platform: prefix subsignals
corelogic -> genlib
generic_platform/get_verilog: pass additional args to verilog.convert
xilinx_ise: disable SRL extraction on synchronizers
Use new 'specials' API
xilinx_ise: import Instance
xilinx_ise: add lock cycle to bitgen
add kc705 platform (partial)
Merge branch 'master' of https://github.com/milkymist/mibuild
kc705: use user_clk (156.25Mhz) instead of sys_clk (200MHz)
kc705: change rotary signal names