cappuccino/ctrl: rename ctrl_mfspr_we_o to ctrl_mfspr_ack_o
cappuccino: add support for multicycle mtspr

This adds the necessary stall logic for mtspr accesses
that are not finished in one clock cycle.
(pronto)espresso/cpu: regenerate
dmmu: register spr write ack

The idea behind this is to delay any upcoming reads by
one clock cycle, thus eliminating the need to bypass
the written data in case the read address is the same as the
write address.
immu: register spr write ack

The idea behind this is to delay any upcoming reads by
one clock cycle, thus eliminating the need to bypass
the written data in case the read address is the same as the
write address.
spram: make bypass optional
dcache: feed ENABLE_BYPASS parameter to spram
icache: feed ENABLE_BYPASS parameter to spram
dmmu: feed ENABLE_BYPASS parameter to spram
dpram_sclk: change behaviour to read-first