cleaned up Si5351C layout
CPLD JTAG header
misc. layout
SPI flash layout
supply zones
clock signal routing
CPLD expansion routing
started back side routing
started rearranging expansion headers
P20 consolidation
finished the trickiest digital signal routing
pushbutton component selection
right angle LEDs
VAA (RF supply) LED
placed SSP1 test points
DRC cleanup
more DRC cleanup
recovered unsaved schematic modifications
new style PCB trace jumper to minimize DRC errors
connected RF shield