R600/SI: Replace writes to SCC with VCC.

When replacing scalar operations with vector,
the wrong implicit output register was used.
R600/SI: Fix assert when instruction has duplicate register operand.

Temporary fix by clobbering iterators.
R600/SI: Use worklist in moveToVALU and make non-recursive.

This is an improved fix for the repeated operand problem.
This somewhat changes the ordering of when operands are legalized,
but I think it's OK.
R600/SI: Move patterns to match add / sub to scalar instructions
R600/SI: Specify S_ADD/S_SUB set SCC and add is commutable
R600/SI: Match adde/sube to S_ADDC_U32/S_SUBB_U32
R600/SI: Match addc to S_ADD_U32.

The carry always goes to SCC.
R600/SI: addc / adde i32 are legal
R600/SI: Implement add i64, but does not yet enable.

Test doesn't actually check the output. I need
to fix add i64 being matched for the addressing
calculations.
Add address space argument to isLegalAddressingMode

On SI, the global buffer instructions have
addressing modes not available for the LDS ones.
Specify address space to isLegalAddressingMode