pcie_driver: Fix compilation warning.
pcie_fpga: Major design cleanup.
- remove most of the dead/commented out code
- remove facilities for DCB/CTL/DLM protocols, as they are obviously
  something very specific to old project
- remove userlogic module; all of the user logic should be connected to
  the Wishbone master - let's be modular and do things The Right Way
- remove DDR_*_FA signals
- remove support for IO transactions; today it's hard to imagine a
  system that doesn't support MEM BARs and even if they do exist
  they are useless to us
- remove debug/led signals - we should either use Chipscope for quick
  debug, or connect some signals to Status registers
- remove obsolete constants is library package
- remove data generator (DG) code, again this is something specific to
  the old project
pcie_fpga: Major cleanup part 2.
- update ISE project file
- commit library change skipped in previous commit
pcie_fpga: Major cleanup part 3.
- update simulation Makefile & Questa waveform defs file
pcie_fpga: Update address assignment for DDR memories to work on all
platforms: k7, a7, ml605.
Merge remote-tracking branch 'ohwr/master'
PCIe_hdl: Move TOP files for standalone PCIe firmware.
Currently PCIe firmware TOP files (bpm_pcie_*.vhd) support both being at
the top of hierarchy for standalone builds, or inclusion in another
projects. But this design creates need for more work because we have to
support 2 options, manually editing UCF files when changing modes and
editing VHDL files.
This patch changes this by introducing top*.vhd files that will
instantiate bpm_pcie*.vhd modules. This change simplifies code and
project hierarchy.
This patch includes support for synthesis. Simulation support will
follow soon.
Changes summary:
- move bpm_pcie_*.vhd files from top/pcie/ to modules/pcie/ directory
- create new top*.vhd files in top/pcie/ directory
- delete INSTANTIATED generic as it's not needed anymore
- update UCF and XCF files
- update XISE project files
- update hdlmake Manifests
Merge branch 'master' of ohwr.org:bpm/bpm-sw
Merge remote-tracking branch 'ohwr/master' into pcie-test
hdl/modules/pcie/bpm_pcie_k7.vhd: remove unnedded generic

The INSTANTIATED generic is not needed after commit 9332adc0a9091
(PCIe_hdl: Move TOP files for standalone PCIe firmware)
hdl/modules/pcie/*: add bpm_pcie package

This will allow for instatiation of bpm_pcie_* components
without the need to specify declare the component
in the design of destination
hdl/modules/pcie/Manifest.py: update Manifest file
hdl/top/ml_605/*_pcie/*: update top PCIe files for ML605

- Removed declaration of bpm_pcie_* component as
    we use the bpm_pcie_pkg package now.
- Changed DDR calibration to FULL instead of FAST.
this is recommended by Xilinx.
hdl/top/pcie/top_ml605.vhd: fix RST_ACT_LOW generic

Override default generic to change reset to DDR3
as active high, as opposed as the default active low