msm: krait-regulator: initialize registers in global space

For the retention mode to work we have to initialize a register in
the global space. This register enables the bimodal switch that controls
whether a cpu is powered by the head switch or an LDO.

Change-Id: I8f7de5f63bbb8af63b118a29d1dec77cd09fc359
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
msm: krait-regulator: Switch to PFM mode under light load

The pmic gang can operate in low power mode when configured
in PFM mode.  In PFM mode the number of phases drop to one
where the gang leader provides all the current.

Use this facility when the combined load decreases below
500mA.

Change-Id: I7e975f811cf1f7cf38300d6c92fd3234d9d0b13f
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
msm: krait-regulator: Use default parameters from the device tree

Parameters like the LDO headroom, default LDO voltage, retention voltage
and the LDO threshold need to be configurable. Accept these values from
device tree instead of defining them locally. Note that since these
are required properties the dts is also updated along with the driver
code.

While at it, update the code to program defualt LDO voltage and
retention voltage for the kraits at probe time.

Change-Id: I41a503e1861f8b895be79b9f01fca1f8e217f55d
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
msm: krait-regulator: Correct pvreg_init() section marking

pvreg_init() should be marked as __devinit (not __init) since it is
referenced from __devinit code.  Fix this.

Change-Id: I129301ecbdf70671ee00086fc6bf22b6b5690fc3
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
msm: krait-regulator: Adjust uA and uV aggregation for offlined
rails

When a core is offlined, it's voltage and current contributions
should be removed from the aggregation that's performed when
setting the voltage and load requirements. This allows our ganged
regulator voltage and phase count to remain no higher than
necessary after we CPU hotplug a core.

In order to support this, introduce regulator_enable() and
regulator_disable() callbacks so that it's possible to control
whether a vreg is in the aggregation list. Also take care to
apply any voltage or current requirements for both disable and
enable. On disable, this allows for lowering the aggregated
voltage and current requirements; on enable, this allows any
changed requirements while the regulator was disabled to be
applied.

Also introduce an is_enabled() callback, since this is required
to support enable().

Change-Id: Ibec8f0182e1edd579f5780d7cc204152491e56fd
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
msm: krait-regulator: fix krait not switching to ldo mode

There is an issue where if a core lowers its voltage such that
the resulting voltage on the pmic gang remains unaffected, that
cpu would not switch to LDO mode even if conditions permit.

Instead of checking for increase/decrease in the pmic max voltage
check if the krait voltage is being increased/decreased and act
accordingly. Note that if a core's regulator is being enabled,
it should act as if its voltage is being increased. This is because
if the gang is running at a low voltage, it should be raised up
before switching others to LDO.

While at it address minor issues
- if setting pmic voltage fails in the voltage increase function
  return with error code immediately
- while iterating over the kraits to find the max voltage, there is
  no need to treat the requesting regulator specially.

Change-Id: I1cbee1d67c0509522f1ecf95c5395bdc5e648c61
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>

Conflicts:
	arch/arm/mach-msm/krait-regulator.c
msm: krait-regulator: fix crashes when switching to ldo mode

The driver is missing configuration for the LDO bandgap. Update the code
to program it via the MDD registers. Consequently update the device
tree definitions to provide physical address of the MDD area.

Also take this opportunity to update the sequence that is used to switch
to BHS. The code needs to enable the BHS and the segments before turning
on the ldo bypass and switching off the ldo. Note that the LDO bypass
needs to remain on while in BHS mode since it is actually a parallel
path to the LDO and helps with power delivery in BHS mode. Update
the diagram to indicate this info.

While switching to LDO mode the BHS segments were left on, update the
code to turn them off.

The current code updates the BHS count, the clock source and the BHS
segments in the init function. There is no reason to do this as the code
that brings up the cpu ends up initializing the same. Consequently
cleanup the code that configures the cpu to be in BHS mode when
a cpu is brought up from reset.

Change-Id: Ic542b55bf509627f4b03a772349093f38b40d86e
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>

Conflicts:
	arch/arm/boot/dts/msm8974-regulator.dtsi
Bluetooth: Disable Sniff on HID ACL(s) if SCO is active

This patch disables sniff support on HID ACL(s) if SCO is active by
updating Link Policy settings. Once SCO is disabled, link policy is
again updated to re-enable Sniff on HID ACL(s). Without this patch
it was seen in presence of SCO, disconnection was observed on HID
ACL(s).

Change-Id: I81e0b3725bdadffe06ddb345afb9de2e042d5f9a
CRs-Fixed: 509616
Signed-off-by: Hemant Gupta <hemantg@codeaurora.org>
Bluetooth: Fix for the l2cap layer crashes while turning OFF BT

-This patch fix a case where while turning OFF BT l2cap channel
 & l2cap conn get deleted in one process context, which preempted
 the another process, where l2cap con was being used while trying to
 disconnect l2cap.  As the result l2cap conn pointer become invalid.
 Later which is leading a crash.  L2cap conn should be guarded by
 spin lock while disconnecting l2cap to avoid preemption which will
 avoid  crash due invalid conn pointer.

-This patch fix list_add crash due to invalid skb pointer.
 & BUG sleep warning as well.

CRs-Fixed: 499732, 504054

Change-Id: I90c5d29cc8728566a420f0dedaf7075846b32d1a
Signed-off-by: Nitin Shivpure <nshivpur@codeaurora.org>
msm: board-8960: Modify SMPS7 min, max voltage limits for 8960ab

PM8921 SMPS7 is the parent regulator for the LDOs which supply
to the Q6 processors. The worst case voltage for Q6 processor
on 8960ab is 1.075V (compared to 1.05V on 8960). Raise the S7
voltage constraints from 1.15V to 1.275V in order to accommodate
the increase in Q6 supply voltage.

CRs-Fixed: 507062
Change-Id: If3e249b6412d141d7108332b43481e127c350bb2
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>