Make memory ports part of specials

This is needed to handle cases where a single memory has ports
in two different modules, and one of these modules is subject
to clock domain remapping. The clock domain of the port in that
module only must be remapped.
bitreverse: fhdl/tools -> genlib/misc
bus/csr/SRAM: better handling of writes to memories larger than the CSR width
genlib/misc: fix import
csr/sram: fix page_bits computation
csr/sram: fix reads on high addresses when word_bits != 0
bus/lasmi: interface definition and crossbar (untested)
examples/sim: rename abstract_transactions to abstract_transactions_wb, use new APIs, remove ASMI
bus/lasmibus: add target and initiator
bus/lasmibus: bugfixes
examples/sim: add LASMI demo
bus: Wishbone -> LASMI bridge (untested)
actorlib: LASMI DMA (untested)
genlib/fsm: fix handling of zero delayed_enter
lasmi: fix minor problems
bus/lasmibus/Crossbar: support cba_shift=0
bus/asmibus: fix slot aging timer
asmibus: remove port sharing
lasmibus/crossbar: better switching policy
genlib/fifo: support records