Align lz4_cache allocations

The original LZ4 source code suggests that that the hash table is
intended to fit entirely into the L1 data cache on Intel processors, but
the code makes no attempt to align its allocations to cache lines. This
is a bug in the original LZ4 code that should be corrected. However, it
does not affect Illumos' implementation.

These allocations are always aligned to a cacheline on Illumos because
the objects are powers of two and the objects are packed consecutively
in page aligned virtual allocations. Unfortunately, the SPL SLAB
allocator does not do this, which causes these allocations to often be
unaligned.

We correct this by explicitly forcing 64-byte alignment. This will
guarentee proper alignment on Intel processors, as well as many others.
LZ4 operations appeared in `perf top -U` as about 1% of total CPU time
on my system prior to this change. It no longer appears on the list.

Signed-off-by: Richard Yao <ryao@cs.stonybrook.edu>