Always turn on ivl synthesis for blif target.
Initial support for NetCondit synth_async.
Fix up NetCondit synthesis to handle complex if/else clauses.
synthesis support for case statements with default cases.
blif code generator support for arbitrary MUX devices.
Cleanup/simplify mux synthesis

Do not create useless NetNet objects for the inputs to the mux.
The synthesizer should already be creating these objects.
Force calculation of blif_nex_data_t width for lib_mux_s1 devices.
NetCase synth async measure width from map, not output.

Make sure the NetMux device has an output that is a net.
blif support for IVL_LPM_FF devices.
Replace svector with vector in synth_sync methods.
Rework synchronous statement synthesis.

This changes the flow of the NetProc::synth_sync method, and
implements the NetBlock::synth_sync better.
Detect and synthesize FF clock enables.

Too bad BLIF doesn't support 'em.
Handle DFF with clock-enable in blif code generator

In the ASIC universe, it is (probably) OK to replace a DFF CE
with a mux of the D input with the Q output. The idea is that
if the CE is true, the DFF latches D, but if CE is false, the DFF
re-latches the current output.
Merge branch 'master' of git://github.com/steveicarus/iverilog