FogBugz #162062: arch/nios2: Add .got section to linker script

This fix the Nios II kernel links to LIBGCC library
functions issue. The GOT PLT needs to be on the beginning
of the GOT.

Signed-off-by: Ley Foon Tan <lftan@altera.com>
FogBugz #162387: Add config options to defconfig to support VLAN tagging

This change enables VLAN tagging to work with the vconfig utility. See
FogBugz #162656 for more details about adding vconfig to the default
file system.

Signed-off-by: Vince Bridgers <vbridger@altera.com>
FogBugz #133693: Fixes for Jumbo frame crash caused by improper sizing of receive buffers

The root causes for the Jumbo frame problems seen were:

1) The driver was enabling Jumbo frames up to 9018 bytes in length (MTU = 9000)
   without allocating the correct amount of receive buffer space. When the
   controller received a packet larger than the smaller receive buffer,
   the controller's DMA overwrote kernel memory, causing code/data
   corruption eventually leading to a kernel crash.

2) The driver was not setting the correct DMA mapping length before
   mapping receive buffers. This led to a subsequent unmapping operation
   using an incorrect mapping length with respect to the one used for
   mapping. As long as the user did not bring down then up the driver, there
   was no problem. This problem only showed up as a result of testing
   MTU changes by cycling the interface up and down through different MTUs.

The fixes implemented for these problems were:

1) Add configuration parameter in the device tree for maximum Jumbo
   frame size. This is needed since the transmit and receive fifos
   sizes are configurable when the cores are created through Synopsys
   Core Consultant. Having this parameter allows DMA I/O memory to
   be conserved as much as possible by only allocating what's required
   for packet receives.

   Example: If the MTU was set to 9000 and the transmit and receive
   fifos were set to 4096 bytes, then a receive buffer size of 16K
   would be used when only 4096 is required.

   The valid range for the C5 SOC is 2000 through 4062, inclusive.

2) Update Documentation text file for stmmac parameters by adding
   "snps,max-mtu" See 1) above for details.

3) Changes to handle proper range checking of MTU in stmmac_change_mtu

4) Use correct DMA buffer length when allocating receive buffers

5) Default Configuration Register 0 settings were changed to
   not enable Jumbo frame by default. 802.3as frame size expansion
   is enabled by default, and Jumbo frame is enabled only if MTU
   size is set for Jumbo frames. This permits receive buffer
   size allocation per current MTU settings.

6) DMA buffer sizes are properly sized for the maximum MTU size configured.

Signed-off-by: Vince Bridgers <vbridger@altera.com>
FogBugz #163712: Add SDRAM ECC/EDAC support to Altera CycloneV board

Firmware to support the EDAC framework for the SDRAM ECC on the
Altera CycloneV board is added in this patch.
- The SDRAM Controller registers are used by the FPGA bridge so
  these are accessed through the syscon interface.
- The interrupts are included in the sdramedac device tree node
  and accessed with the platform functions.
- The configuration of the SDRAM memory size for the EDAC framework
  is discovered from the memory node of the device tree.
- Documentation of the bindings in devicetree/bindings/arm/altera

V2: Implement review changes.
- Fix copyright.
- Call edac_mc_free() if error on devres_open_group().
- Remove pr_debugs.
- Fix spacing in calculation for readability.
- Add platform_set_drvdata() in alt_sdram_mc_remove().
- Add of_match_ptr() around .of_match_table element.

V3:
- Replace pr_debug() with dev_dbg().
- Remove /r line endings.

V4:
- Check return code of regmap_read() in probe.

V5:
- Clear regmap_read() variables before use.
- Check return code when looking for memory size.
- Include attribution in copyright.
- Enable IRQ after successfully adding memory controller.

V6:
- Rename functions and macros from ALT to ALTR
- Cleanup of code to reflect Linux conventions.
- Replace MODULE_ALIAS with MODULE_AUTHOR("Altera Corporation");

Signed-off-by: Thor Thayer <tthayer@altera.com>
FogBugz #119760: Document Designware SPI driver bindings

The community Memory Mapped Designware SPI driver is not
currently documented so it is added here.

V2:
  Use generic interrupt description instead of GIC specific.

V3:
  Cleanup of extra lines & compatible description.

V4:
  Addition of clock source.

Signed-off-by: Thor Thayer <tthayer@altera.com>
FogBugz #163905: Support Denali NAND driver on socfpga platform

This patch addresses a few bugs and features in the Denali NAND driver on the socfpga platform.

First the bugs:

- Reading ONFI parameters would cause a timeout, because the code sent the wrong
commands to the controller/device.  That was fixed, and in the process, code was
added to wait for the appropriate interrupt.

- When using the JFFS2 file system, a bug was discovered in the write OOB
data function, whereby the controller was left in SPARE mode causing
subsequent page reads to fail.  The write OOB function was modified
so that the controller is left in MAIN access mode.

Now the features:

- The Denali NAND controller in the socfpga platform has hardware ECC, and several
status bits are different because of that.  A patch from Jamie Iles <jamie at jamieiles.com>
was used as the basis for supporting hardware ECC in the code.

- The device tree and documentation were modified to support hardware ECC.

- One of our test socfpga boards had a NAND chip which was locked by default.  To support
writing to the chip, the UNLOCK1 and UNLOCK2 commands were implemented.  The nand_unlock
calls were added as well.  (Note, the mtd layer has _lock, _unlock, and is probably a
better place to implement this functionality than the nand driver).

- The mtd_device_register call was replaced with mtd_device_parse_register so that
device tree partitions are setup by the mtd layer.  Example partitions were added
to the device tree.

- In the process of supporting our specific controller configuration, duplicate
definitions of bad block table descriptions were removed from the denali code.  They
also exist in the nand driver code.

Signed-off-by: Graham Moore <grmoore@altera.com>
FogBugz #163802: arch/nios2: Copy FDT from init memory to regular memory

If the supplied DTB is builtin into kernel, it is in __init memory and
will eventually be destroyed after bootup. But if drivers are loaded as
modules, they still need to access the DTB entries after the kernel has
started. Therefore, the DTB is moved to a new allocated area.
Thanks Jeroen Van den Keybus for the fix.

Signed-off-by: Ley Foon Tan <lftan@altera.com>
FogBugz #163307: align f2sdram driver with hw support

The read, write, and command ports on the fpga2sdram
bridge can only be reconfigured if there are no
transactions to the sdram during the reconfiguration.
Currently, this guarantee can only be made by code
running out of onchip ram before Linux is started.  Therefore,
this driver only supports enabling and disabling of the
ports that have already been configured.  Since the
driver cannot determine the port configuration in all
cases, the device tree must be populated with masks for
all of the ports.

Signed-off-by: Matthew Gerlach <mgerlach@altera.com>