mdss: ppp: Fix arithmetic error

Width was not calculated properly. This would cause ppp to go
into bad state and hang.

Change-Id: Ie70db84802d668ea169cbb42025cb3e5aab230da
Signed-off-by: Terence Hampson <thampson@codeaurora.org>
msm: mdss:  Set rotator output format as pseudo planar 420

Set rotator output format for planar 420 as pseudo planar 420.
Configure BWC output format as MDP_Y_CRCB_H2V2 when
input color format is MDP_Y_CBCR_H2V2.

CRs-Fixed: 549326 552372 552375
Change-Id: I9c39ab3d8a867909853ffd6ecc2120ab160914d1
Signed-off-by: Pawan Kumar <pavaku@codeaurora.org>
msm: mdss: Correctly update pwm configuration

Backlight pwm was incorrectly updated while changing the backlight
level. We need to disable the pwm configuration before updating
it with the updated value.

Change-Id: Ie027c26a614c6bb0ffdc51218cf4c81b26ceb736
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
Signed-off-by: Casey Piper <cpiper@codeaurora.org>

Conflicts:
	drivers/video/msm/mdss/mdss_dsi.h
msm: mdss: Change the Alpha scaling type to bilinear

Currently, for Alpha plane the filter used is nearest due to which
there is an aliasing effect. Using the same filter as graphics core
which is bilinear, the aliasing effect is avoided.

CRs-fixed: 517627
Change-Id: Ifb4629ddcea1ac447d151469b1f56e3400b7fac0
Signed-off-by: Sree Sesha Aravind Vadrevu <svadrevu@codeaurora.org>
mdss: display: add mdp core clock to dsi clock control

Since mdss interrupts are generated in mdp core clock domain,
mdp clock need to be enabled to have dsi interrupt be delivered
during dsi dcs command send and receive. Request of bus bandwidth
also needed to allow dsi controller to fetch dcs commands over
AXI bus.

CRs-fixed: 516172
Change-Id: I6e10cc5a193c9eb06803637e0432ec72f069377b
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Revert "Debug: This helps debug iommu issue inside mdp ppp."

This reverts commit dc1768371b49b47f5ddceed240028ef7359dfd23.
Issue this was debugging has been fixed.

Change-Id: Ifdd36ad6d3614bb16f47546a719ff64a724cd97d
Signed-off-by: Terence Hampson <thampson@codeaurora.org>
msm: mdss: Fix watermark level calculations for pipe updates

Watermark (wm) levels for active pipes are calculated and set for every
surface update regardless of pipe parameters are changed or not. In the
current implementation if reserved MMBs are not changed compared previous
frame then wm levels are reset to zero. This is not a correct behaviour
and may lead to under-runs. Fix this by setting wm levels based on
allocated MMBs.

Change-Id: I857c161f7203b64411e9345553f88c48f7726ee2
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>
msm: mdss: Enable fixed MMBs support for RGB pipes

RGB pipes in some of the chip-sets are statically tied to dedicated
Memory Macro Blocks (MMBs) out of common shared memory pool. These MMBs
cannot be used by other pipes. Enable support for this fixed MMBs by
parsing indexes from device tree and reserving fixed MMBs first before
general pool is used.

Change-Id: Ic4bc7fa790f430a2853719fec7fd849149bc6976
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>
msm: mdss: fix the dma-s register offset on 8x10

The register offset for DMA-S pipe was incorrect.

Change-Id: I2ab3ad83371b399cd7c625948198b3f397866750
Signed-off-by: Xiaoming Zhou <zhoux@codeaurora.org>
msm: mdss: hdmi: Proper DDC power off sequence

Shutdown the power for DDC (Display Data Channel) module only
after HDCP (High-bandwidth Digital content Protection) module
has been turned off as HDCP continue to use DDC line until it
is turned off. Also, no need to check for DDC hardware status
on HDCP off as once the cable is disconnected it will not be
updated.

Change-Id: Ic5b8c2d6c4a43bf7d0ed0d420690b7e84bbe3b6c
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
msm: mdss: sync point factoring to allow async signaling

Refactor sync point implementation by using a commit thread to handle
all commits for better performance. By using commit thread we can also
allow unblock user space to program new frames while the update is still
in progress. Allow for async notifications to be done when frames are
flushed (new frame can be programmed) and frame is done (new frame can
be displayed).

Change-Id: I0952f3f0ea9273a92c74fa42cd3ca9c6f9d042f3
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>

Conflicts:
	drivers/video/msm/mdss/mdss_fb.h
	drivers/video/msm/mdss/mdss_panel.h

Conflicts:
	drivers/video/msm/mdss/mdss_fb.c
	drivers/video/msm/mdss/mdss_fb.h
msm: mdss: implement asynchronous frame events

Asynchronous frame events from MDP allows commit thread to be unblocked
once the frame contents have been flushed to MDP HW and new frame can be
programmed while waiting for DMA transfer to complete.

Change-Id: Ica878f9d06ab0cc5260ad412815dcbd8ae391767
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>

Conflicts:
	drivers/video/msm/mdss/mdss_mdp.h
	drivers/video/msm/mdss/mdss_mdp_overlay.c
msm: mdss: unregister command mode vsync handlers on stop

When command mode panel is being stopped, any vsync handlers that are
still pending should be removed before shutdown sequence. If this is
done afterwards VSYNC_TICKS update may cause the clock to continue
running after clocks have been shutdown and may lead to MDP hang.

Change-Id: I149390413326b21ddf608e7fe5a31b3a57abe50b
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>