general-cores: update submodule referenced commit
wb_fmc516/*: add data/clock topology for fmc516
wb_fmc516/*: flexible clock/data chain routing
wb_fmc516_test/: add simple sim files
various: small fixes and identation issues
wb_fmc516/*: add trigger buffers and small fixes
wb_fmc516_tb.vhd: update port definitions
wb_fmc516/*: add slv adapter, leds pulse and wb fanout

Also, related testbenches and component declaration
files were modified in order to adhere to the new
wb_fmc516 port specification
wb_fmc516/*: add wishbone register interface
wb_fmc516/*: adc_iface rewrite and general assignments
custom_wishbone/*: small fixes
wb_fmc516_test/*: update testbench and related files
wb_fmc516/*: update register interface, data streaming and small cleanup
wb_stream/*: update wishbone stream converter and related files
wb_fmc516_test/vhdl/*: small naming fixes and update port definitions
wb_fmc516_test/verilog/*: initial verilog testbench (with errors)
wb_fmc516/* and wb_fmc516_test/*: fix multiple drivers typo
.gitattibutes: add binary filter for dbe.vhd
wb_fmc516/*: add sdb structures, spi and i2c interfaces

Still missing interfaces with LMK (microwire), VCXO (i2c)
and One-wire
wb_fmc516_test/*: small fixes and updates