Changes here include a redo of the clocking init, and detection of if the dsp can boost.
A Correction of the CPU clk to 212 Mhz, rename DSP clock to be SYS. Is much more accurate.

Corrected strcpy to strlcpy.

Added the ADSL reset bits and the IRQ bits.
Added some resources to the mix.

Added a dsp host translate function pointer, so the relevant way of accessing the DSP memory can be used.