net: axi_emac: Check if phy was correctly detected

As tsec and fm drivers checking phydev->link
ensure that u-boot don't try access device if link is not ready.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
net: emaclite: Remove duplicated comment

Trivial fix.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
net: emaclite: Check if phy was correctly detected

As tsec and fm drivers checking phydev->link
ensure that u-boot don't try access device if link is not ready.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Revert "ARM: use r9 for gd"

This reverts commit fe1378a961e508b31b1f29a2bb08ba1dac063155.

The reason for reverting this patch is that it is breaking
example applications where stub is still using r8
instead of r9. This change wasn't the part of origin patch
and also there is any problem with FreeBSD which our
u-boot also supports.
It is safer to revert this patch for now.

For more information look at:
http://lists.denx.de/pipermail/u-boot/2013-November/167389.html

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Provide DIV_ROUND_CLOSEST macro

Provide the DIV_ROUND_CLOSEST macro - taken from the Linux kernel - in
common.h

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
zynq: Provide a framework to read clock frequencies

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
serial_zynq: Migrate to Zynq clock framework

Remove hard coded frequencies and use Zynq's clock framework to obtain
the UART clock frequency.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
zynq: serial: Simplify serial driver initialization

Define both serial uarts in the driver and return
default uart based on board configuration.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arm: zynq: timer: Migrate to zynq clock framework

Remove hardcoded frequencies in favor of Zynq clock framework.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
spi: zynq_qspi: Remove hardcoded frequencies

Remove hardcoded frequencies in favor of using the zyng clock framework.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
zynq: Remove hardcoded CPU clock frequency

Drivers have been migrated to use the zynq clock framework rendering
the hardcoded CPU frequency defines unused.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
net: zynq_gem: Move RCLK details out of driver

The GEM driver should not need to know about Zynq specific details of
RCLK related registers and bitfields in the SLCR. Move those details to
the slcr driver.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
net: zynq_gem: Calculate clock dividers dynamically

Remove hard coded clock divider setting and use the Zynq clock framework
to dynamically calculate appropriate dividers at run time.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
common: Add new clk command

Command provides just dump subcommand for showing clock
frequencies in a soc.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
zynq: Implement dump clock command

Enable and implement dump clock command which shows
soc frequencies.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>