Supply BigInt constructors for Bits/UInt/SInt

Conflicts:

	src/main/scala/Bits.scala
	src/main/scala/SInt.scala
	src/main/scala/UInt.scala
Work in progress on reference-chip
Remove isSigned
Fix(?) << and >> width inference
Make ROMs synthesizable; remove O(n^2) code

"initial" => "always @(*)"
String => StringBuilder

Conflicts:

	src/main/scala/Cpp.scala
	src/main/scala/ROM.scala
	src/main/scala/Verilog.scala
Improve Mux1H QoR

The previous implementation did not take advantage of the one-hot
property of the input, resulting in a priority encoder.

I also removed some redundant constructors (leveraging Vec <: Seq).
Improve PriorityEncoderOH QoR

Exposing a higher-level priority encoder structure improves QoR for
Synopsys DC, at least.  (It also results in fewer Chisel nodes.)
fix bug in Cpp.scala when block has zero strings
Handle incorrect bus extraction in the front-end

Things like foo(0,1) (instead of the correct foo(1,0)) result in helpful
error messages, rather than incorrect Verilog.
For C++, throw exception on assertion failure

This is more useful than just calling abort() as the user can catch
std::runtime_error for special handling.
Add Mux1H support for zipped Seq[(Bool, T)]
Make Mux1H interface more generic
Add Module.current API call to get current Module

In the context of a Module, Module.current is equivalent to "this".

Conflicts:

	src/main/scala/Module.scala
Provide hashCode, equals defs for Module

This enables Modules to be used as keys in Sets/Maps.
Add Bool.DC factory method to create a don't-care

Conflicts:

	src/main/scala/Bool.scala
Make Vec constructor interface more permissible

Use Iterable instead of Seq

Conflicts:

	src/main/scala/Vec.scala
Misc. changes to make reference-chip compile