top:add Manifest, top hdl and sdc files
syn:add Makefile, Manifest.py, veatar project files
ip-cores:add vme64x core temporarily till I have the repo in ohwr
git:adding new files to
change the pin assignment of HDMI and display
add new plls and butis module
ip-cores:add submodule legacy-vme64x-core
ip-core:remove the vme64x-core
add legacy-vme64x-core
qsf:change the path to the legacy-vme64x-core
vetar/syn/:Makefile prog, will program the FPGA
update legacy-vme64x-core, sdb : add sdb to wishbone master
vetar: add negative logic to the input lemo
vetar:add pin lemo input
vetar.qsf:change signalTap
legacy-vme64x-core:update of the submodule
merge branch vetar